Articles by Steve Sandler

The voltage regulator module (VRM) contributes system level noise in several ways. Power integrity (PI) engineers tend to focus on transient voltage noise related to high-speed dynamic current. Many PI simulators ignore the VRM noise and use an ideal resistor and inductor model to represent the VRM. This overly simplistic approach misses many potential system level issues.

Obtaining accurate measurement data requires either accurate knowledge and accounting for the probe and fixture influence OR calibration methodology to remove these effects prior to measurement.

When you make a 2-port shunt through measurement using a commercial vector network analyzer the measurement includes an undesirable ground loop. Left uncorrected, the ground loop introduces significant errors. This paper shows how to solve this problem.

The power electronics engineer and the power integrity engineer share a common goal: provide the system with the correct voltages, currents, and noise characteristics to achieve the desired performance. Unfortunately, they do not share much else. They generally use different tools, vocabulary, and figures of merit. As a result, both sides lose.

Target impedance has become a standard tool when designing a power distribution network (PDN). It establishes a limit to the highest impedance the power rail on the die should see looking into the PDN. If the PDN impedance stays below this limit, even the worst-case transient current from the die will generate an acceptably low rail voltage noise.

This paper reviews four levels of VRM models that VRM designers, board level interconnect designers, semiconductor designers, and product managers often use to explore design tradeoffs throughout the PDN system. The choice of which one to use involves considering engineers’ levels of expertise and what problems they expect to analyze. Some tradeoffs and relative merits of the models are described.

VRMs and VRM controllers are often selected based on size, efficiency, price, or a relationship with the manufacturer. This often leads to a poor VRM selection, requiring additional engineering resources, greater time to market, as well as, higher BOM costs to correct the deficiencies. In this article, we evaluate the choices, define some useful figures of merit, and provide specific selection suggestions.

A common design technique for power distribution networks (PDN) is the determination of the peak distribution bus impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance. In theory, the allowable target impedance is determined by dividing the tolerable voltage excursion by the maximum change in load current.

A negative coupling coefficient between decoupling capacitors is expected to result in lower inductance.  While this is generally the case, this can also result in much higher PDN impedance.