Featured Stories

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How Interconnects Work: Bandwidth for Modeling and Measurements

Modeling and measurement of digital serial interconnects is usually done in the frequency domain. That means that the minimal and maximal frequencies (or bandwidth) should be defined even before the analysis or measurement begins. This post introduces a simple and practical way to identify the bandwidth with a numerical analysis of defects in a single bit (SBR) or single symbol response (SSR).


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224 Gbps Link Systems: Modulation vs. Channel vs. FEC

What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.


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Which Discontinuities are Small Enough to Ignore?

Understanding and minimizing discontinuities is increasingly important as serial links become both shorter and faster. Applying the old edge rate to roundtrip relationship to the modern era, Donald Telian in this article offers a rule-of-thumb to help gauge which interconnect structures, and hence discontinuities, to care about – and to what degree.  


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Book Review: Signal Integrity in Practice by Don Telian

If you’ve just started on the path of designing high-speed serial links or have designed dozens of your own, Don Telian’s Signal Integrity in Practice is the book that will accelerate your engineering judgment and possibly save you from multiple design spins. Eric Bogatin takes a closer look at what he considers a must-have book for new and experienced engineers.

 


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What to Expect in a Multi-Drop Bus

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.


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