Articles Tagged with ''DesignCon 2025''

Gore Cover 8-19-25.png

Path to 400G May Require Alternative Architectures

DesignCon 2025 Best Paper Award Winner

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.



Read More
DesignCon Paper Summary Cover 8-12-25.png

Innovative Layout Optimization Methodology and Via Routing Pattern to Enable UCIe-36 Gbps in Organic Interposer

DesignCon 2025 Paper Summary

This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.


Read More
DesignCon Paper Summary 8-5-25.png

Innovative Interposer Solutions for HBM3/4: A Path to 12.8 Gbps

DesignCon 2025 Paper Summary

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.


Read More