July 25, 2017

Sponsored by: GigaTest Labs

Giga Test Labs

Featured Article

5 Leading EDA Tools for EMC/EMI Design Challenges

By Pat Hindle

This article reviews the capabilities, new functions and application examples of 5 leading software tools for EMC/EMI design challenges including Altair/FEKO, ANSYS, CST, Keysight and NI/AWR.


Featured Article

Practical DDR Testing: Compliance, Validation and Debug
By David Maliniak and Dr. Patrick Connally, Teledyne LeCroy

This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.



Rohde & Schwarz

Verifying power integrity for DDR memories
By Rohde & Schwarz

The R&S®RT-ZPR20 power rail probe is a specialized oscilloscope probe for very low-noise measurements on power rails.




IDT's Flexible Timing Solution Provides Valuable Design Margin for Multi-Lane Interfaces


IDT announced a highly-programmable clock generator and jitter attenuator IC featuring less than 200 fs of phase noise, providing valuable system design margin for 10 Gbps interfaces in wireline and wireless communication networks.





High Speed Digital Symposium

Eric Bogatin

Dr. Eric Bogatin, Editor of Signal Integrity Journal and Dean of the Teledyne LeCroy Signal Integrity Academy, will chair the symposium. This special event is sponsored by Signal Integrity Journal and requires a conference pass.


View Full Program and Register


Signal Integrity Webinar



Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.

Browse webinars here.

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