Items Tagged with 'roughness'

Copper foil and oxide roughness are also major drivers of insertion loss behavior. As discussed in Part 1 of this article series, the first crucial step to efficacious design and development is understanding how the dielectric material attributes are to be carefully considered when assessing impedance and insertion loss performance. This article by Keshav Amla highlights the importance of considering roughness attributes in this assessment, ensuring a well-rounded approach to addressing impedance and loss, as well as skew, a signal integrity concern of ever-increasing importance.

Designing the right PCB stackup can make or break product performance. If the product has circuitry that is impedance and transmission loss sensitive, then paying attention to conductor surface roughness is paramount. Sometimes, however, the roughness of adjacent reference plane(s) is overlooked. If the adjacent high-speed signal layer uses smoother copper than one or both reference planes, a higher insertion loss than expected for that layer will occur and possibly cause a product to fail compliance. So, how is this determined before finalizing the stackup? Read on to find out.

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.