Items Tagged with '100 Gb/s'

This paper presents two modeling methodologies for ADC-based SerDes that mitigate IBIS-AMI architectural misalignments, and a corresponding model correlation methodology.

Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.