Recently, Signal Integrity Journal asked Ken Willis, Product Engineering Architect, Signal Integrity at Cadence about product development, business challenges, and the latest developments in SI/PI design. With more than 25 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits, Willis had a variety of insights on the topics. Prior to joining Cadence, he held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity. Here is a summary of the conversation, edited for length.
SIJ: How has your approach to product development changed, if at all, as regards signal integrity and power integrity products?
Ken Willis (KW): I think the major difference is with respect to integration with the design process. Historically, users were focused on simply being able to analyze their design. Now they want to be able to instantiate changes to the design as well. And the more advanced customers are shifting more emphasis to up-front feasibility and trade-off analysis and deriving constraints to drive the design process.
SIJ: What are the greatest challenges you think Cadence faces technically?
KW: From a signal integrity standpoint, it is speed and capacity. System-level design has lagged chip-level design from this perspective. Customers want full design-level PI and SI analysis coverage, taken to a significantly greater level of detail. Running everything on one user’s PC has quickly become impractical. Users want to run many sweep simulations upfront to understand the design space on the front end, and detailed post-layout verification sims on the back end, with in-design analysis in between. Multi-core, multi-threaded processes run across several big machines will become the norm, trending towards more and more cloud computing.
SIJ: What are the challenges from a business perspective?
KW: Finding and keeping talent will always be an ongoing challenge. That is the ante to play in the EDA space. But I think in the SI/PI realm now, the business challenge is displacement. Most companies have a methodology and SI/PI toolset in place at this point. To come in and sell tools, you must displace something that is entrenched, which you can only do by providing something that offers a major distinguishing advantage. To be able to come up with those big advantages continuously is a challenge.
SIJ: Can you talk a bit about Cadence’s structure? How do the different business units or teams interact in the product development/launch process?
KW: The different business units at Cadence have historically been largely independent, but we have seen the synergies come into play over the past several years. A couple of years ago we combined our custom IC and package/PCB business units together, and you see that paying off now as those lines blur and customers do things like heterogeneous, multi-die module design, combining a traditional IC front end with a historically package-based back end. The other place we see significant synergies is between our IP and systems business units. The IP unit heavily uses our system analysis SI tools to perform IBIS-AMI modeling and system-level simulation of the test systems we design and build to test our IP running in the multitude of interfaces we support. That synergy is starting to naturally flow out to joint IP/ systems customers, to their benefit.
SIJ: Why would someone want to work at Cadence?
KW: I think the most attractive thing about working at Cadence—besides getting to work with and learn from lots of smart people—is that we get to work every day with the top electronics companies in the world. We get to see what they are doing, what their challenges are, and collaborate with them to solve the biggest challenges in our industry today. We are in the thick of everything exciting that goes on in the electronics world across every market segment. And being the only company in the world that develops IP as well as chip, package, and PCB design and analysis tools gives us a unique vantage point from which to observe the innovations and changes that take place daily at Cadence.
SIJ: Cadence does a significant amount of customer training. How has that evolved over the years? What are you finding works best for your customers?
KW: Customer training has evolved to provide more video-ondemand content, which is the way many people—especially the younger engineers—prefer to learn. And that is great because it provides more training access to more people. But I am still old-school from the standpoint that if I were a hardware manager that just spent a lot of money on EDA tools, I would want everybody in one place for that initial onsite classroom training experience. Then all the video content could be used for that next drill-down on level of detail in specific areas.
SIJ: Tell us about one of your latest products for SI/PI design and analysis.
KW: In the PI space, one of the highlights has been the Cadence Allegro® PowerTree™ Technology, which provides a schematic-level view of the power rails, allows up-front analysis to be run in the design process, and automates PI analysis setup downstream in the physical layout. This has had methodology implications in that it enables team-based PI design and analysis across the design engineer, layout designer, and analysis engineer. In the SI space, we have seen a constant evolution of standards-based design. A large chunk of the SI activity has boiled down to two categories; memory interfaces and serial links, both using the latest preliminary standards before they are published. And from DDR4 onwards, we have witnessed a trickle-down of serial link modeling and analysis methods into the memory interface space. For example, we see serial link channel simulation methods to simulate DDR4 and DDR5 interfaces for bit error rate performance, using IBIS-AMI to model advanced, adaptive equalization. And the modeling of equalization gets pushed to an even further extreme as you move into PAM4 and 100+ Gbps serial links.
SIJ: Can you share your product roadmap for SI/PI related products?
KW: Not specifically. But what you will see from Cadence over the next couple of years in the SI/PI area will be largely combinatorial, integrating areas together that have long been siloed. Examples of this will be more holistic, joint custom IC and package/board methodologies. Board design will leverage into system design, PI analysis will continue to be integrated into detailed SI analysis, and platforms will be established for design engineers, layout designers, and analysis engineers to effectively collaborate and leverage each other’s work more efficiently. The unique combination of IP and SI/PI analysis at Cadence will accelerate and enable us to deliver standards-based solutions ahead of the market need. This will all be underpinned with high performance and cloud-based computing solutions. We have been working on harnessing the power of machine learning for several years, and recently announced programs will accelerate our machine learning initiatives to make our tools easier and more intuitive to use. This will all converge to shine light in areas that we have previously only been able to wonder about. It will be an exciting time.