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September 10, 2019

Sponsored by: EDI CON ONLINE



Guard Traces: Love Them or Leave Them?

By Eric Bogatin and Bert Simonovich

Ask any engineer how to reduce the cross talk between two signal traces and the most common answer will be to add a guard trace. This should be the last resort, not the first choice. Guard traces can often introduce more problems than they solve.  Find out why in this article. 


Apples-to-Apples Material Characterization for High-Speed PCB Design

By Bill Hargin and Don DeGroot

Engineers invest tens to hundreds of thousands of dollars in signal integrity simulation software—the goal being to gain an accurate understanding of how signals are going to behave in the final product. But how do you do that early in the design process without reliable, verifiable electrical properties for the dielectrics incorporated into your design?

News Feature2

Open Eye Consortium Announces Single-Mode Specification for Datacenter Applications

The Open Eye Consortium (Open Eye MSA) announced the availability of its 53 Gbps single-mode specification to its members, which defines the requirements for fully analog PAM-4 solutions for 50G SFP, 100G DSFP, 100G SFP-DD, 200G QSFP, and 400G QSFP-DD and OSFP single-mode modules.

News Feature1

ECOC Market Focus Speakers to Identify Key Role of Optical Communications to Deliver New Technologies

European Conference on Optical Communications Exhibition (ECOC), Europe’s largest optical communications exhibition, has announced the agenda for its popular Market Focus which will feature exclusive presentations focusing on 400G and 800G, fibre for 5G and New Markets including 3D sensing.


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EDI CON Online

High-Speed Interconnect Design and Correlation at 112 Gbps PAM: How does this affect me?

This SI/PI Technical Session on September 12 at 2:30pm ET presented by Scott McMorrow, will detail an interconnect design process from concept and design through simulation, testing and correlation to high-volume manufacturing. He will explore how the correlation between simulated and tested and measured results builds confidence in a design process.

Learn more about the details of this session and
Register for FREE today.



Best Practices for Interpreting Power Integrity Measurements

Modern electronics, from automotive to Internet of things, and everything in between, present many power integrity challenges. The performance of the high-speed circuits, including reference clocks, LNAs and transceivers, is dependent on power supply noise. This webinar provides expert advice on the best methodologies for performing low noise measurements as well as explains how to identify and correct power-supply related issues. Register and join us on September 18th!


Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.


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