Items Tagged with 'de-embedding'

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s

Stefaan Sercu, Samtec Signal Integrity R&D Engineer, recently presented “Impedance Corrected De-Embedding,” which discussed the advantages of impedance corrected de-embedding over standard 2X through de-embedding, here are some highlights of his talk.

Wondering about the practical uses of the proposed IEEE P370 standard? This  paper shows some applications of the draft IEEE P370 standard in order to demonstrate its effectiveness for interconnect measurement.

The fixtures used to characterize interconnects in complex systems can have a significant effect on the measured data, read on to get the background and perspective on IEEE P370. Check out this Outstanding Paper Award Winner from EDI CON USA 2018.