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The articles and columns contained in this section come from members of the Signal Integrity Journal community with expertise in test & measurement.

Why On-Die Power-Rail Measurements are Important

For this project, we will use an Atmel 328 microcontroller demo board, prepared with firmware to control it explicitly for our purposes, and with coaxial cables connected between the I/O pins and the input to the active probes of the scope. This interconnect provides a high bandwidth transmission line path for the signals.

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Bandwidth, Current Load and Power-Rail Measurements

How do you achieve high bandwidth in your measurements while minimizing current load on your DUT? Given that your DUT is a power rail, you really don't want to draw too much current from it., or your measurement system will distort the rail. But these two measurement criteria are at loggerheads with each other. It's a quandary, and it has to do with the fundamental nature of signals on interconnects.

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Mitigate RF Pickup In Power Rails

Measuring the noise on a power rail seems to be a straightforward task. However, there are some basic pitfalls that can cause incorrect, or even downright strange, results. Let's look at one of these challenges: RF pickup. We'll demonstrate the effect of RF pickup on a power-rail measurement, and then we'll show you an effective means of mitigating that effect.

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Introduction to PCIe 4.0 Electrical Compliance Test

Now in its fourth generation, which sports data-transfer rates up to 16 Gb/s, Peripheral Component Interface Express standard (PCI Express, or PCIe) requires challenging physical-layer test requirements (Figure 1). We've covered electrical compliance test for PCIe 3.0 in some detail, but with the test specifications for PCIe 4.0 rounding into shape, it's time for a deep dive into electrical compliance test for this ubiquitous peripheral interface protocol.

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Practical DDR Testing: Compliance, Validation and Debug

DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems.  This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
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