Articles by Mike Resso

Traditional data-center physical layer architectures have undergone a significant transition due to the growth of east-west traffic within the data center for AI/ML cluster applications. This data growth has driven enormous demand for throughput in both chip-to-chip and chip-to-module channels. In this paper, which was awarded Best Paper Award at DesignCon 2025, the authors explore various physical layer design improvements through simulation and modeling tools.

This paper, awarded the Best Paper Award at DesignCon 2024, explores what is meant by bandwidth during the standardization process, the implications of test and verification attached to certain bandwidth requirements, as well as differences between acquisition range, band limited filters, and s-parameters for time domain processing. 

Emerging 100 Gigabit Ethernet and 400 Gigabit Ethernet requirements for communication networks have put increasing demands on Internet infrastructure. New methods of design, validation, and troubleshooting to optimize high speed digital channels are being employed in the R&D laboratory. This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.