Abstract: 

The rapid growth in Data Centers, AI, and supercomputing demands significantly faster edge rates at the package and PCB levels, necessitating superior power delivery network (PDN) solutions. While traditional VRMs and bulk capacitors dominate at lower frequencies, the impact and effectiveness of embedded capacitors in high-current PDNs remain critical for achieving high performance. This paper explores various embedded capacitor technologies and their layout considerations within PCB and package stackups. Through detailed simulation and measurement, we analyze the influence of embedded capacitors on system performance, noise reduction, and power delivery efficiency in AI/datacenter applications. We specifically investigate how embedded capacitors impact large signal phenomena, validating findings through both measurements and simulation, and present methods for effectively modeling small signal analysis with these components. We also discuss manufacturing challenges and examine the impact of lateral versus vertical power delivery systems; specifically, we address how vertical power, while more efficient and higher performance due to proximity to the chip, removes the ability to place backside decoupling. This work provides comprehensive insights into leveraging embedded capacitors to optimize PDN design for next-generation ASICs.


Extended Description:

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The rapid growth in Data Centers, AI, and supercomputing demands significantly faster edge rates at the package and PCB levels, necessitating superior power delivery network (PDN) solutions. While traditional VRMs and bulk capacitors dominate at lower frequencies, the impact and effectiveness of embedded capacitors in high-current PDNs remain critical for achieving high performance. This paper explores various embedded capacitor technologies and their layout considerations within PCB and package stackups. Through detailed simulation and measurement, we analyze the influence of embedded capacitors on system performance, noise reduction, and power delivery efficiency in AI/datacenter applications, addressing the question of how effective power delivery is with embedded capacitors in a data center application. We specifically investigate how embedded capacitors impact large signal phenomena, validating findings through both measurements and simulation, and present methods for effectively modeling small signal analysis with these components, thereby analyzing large and small signal phenomena and the corresponding way of simulating them. We also discuss manufacturing challenges and examine the impact of lateral versus vertical power delivery systems; specifically, we address how vertical power, while more efficient and higher performance due to proximity to the chip, removes the ability to place backside decoupling. This directly addresses impacts to power delivery from a lateral delivery system vs. a vertical delivery system with embedded capacitors in the package or PCB stackup. This work provides comprehensive insights into leveraging embedded capacitors to optimize PDN design for next-generation ASICs, contributing to the development of decoupling embedded capacitors and how they can impact PDN design.


Purpose Statements:

  • How effective is the power delivery with embedded capacitors in a data center application?

  • Development of decoupling embedded capacitors and how they can impact PDN design

  • Are there impacts to power delivery from a lateral delivery system vs. a vertical delivery system with embedded capacitors in the package or PCB stackup?

  • The technological growth in Data Centers, AI, Graphics, and Super-Computing has pushed significantly faster edge rates both at the package and PCB level. This puts a higher demand on addressing and finding better power delivery solutions to support these next-generation ASICs. 

  • At lower frequencies, VRMs, bulk capacitors dominate the PDN, but where do embedded capacitors impact the PDN? How effective are they when added in the PCB and/or package stackup?

  • What embedded capacitor technologies are available for today’s demanding power delivery applications

  • What are the Layout considerations and strategies with using embedded capacitors in a pcb and package?

  • Analyzing large and small signal phenomena and the corresponding way of simulating them

  • Investigate through simulation and measurement how embedded capacitors in a PCB and package can improve our system performance and lower our noise.

  • Discuss manufacturing challenges with stackup design using embedded capacitors

  • How do embedded capacitors improve or impact large signal phenomena, this will be explored with measurements and simulation

  • How to effectively model small signal analysis with embedded capacitors


Key Takeaways:

  • Can embedded capacitors provide sufficient benefits to overcome space constraints in vertical power delivery systems, given the inherent limitations on back-side decoupling in such configurations?

  • This paper seeks to investigate how embedded capacitors impact both large and small signal phenomena in high-current PDNs, providing validated modeling and simulation methods

  • This work aims to comprehensively analyze the role of embedded capacitors in optimizing Power Delivery Network (PDN) design for next-generation AI/datacenter ASICs, considering their impact on system performance, noise, efficiency, and the implications of lateral versus vertical power delivery systems.