Items Tagged with 'PCIe'

The PCIe standard has successfully doubled its per-lane bandwidth across seven generations while maintaining full backward compatibility. PCIe Gen8 continues this legacy, targeting 256 GT/s per lane using PAM4 signaling. However, with each new generation, achieving backward compatibility within the same mechanical envelope becomes increasingly complex. Follow along as Abhijit Wander explores how sustaining bandwidth scalability beyond Gen7 may ultimately require both electrical and mechanical innovation rather than purely material or footprint optimization.

The version 0.3 development milestone marks the completion of the first review draft of the specification and confirms that PCI-SIG is on track for a full PCIe 8.0 specification release by 2028.

Skyworks introduces the SKY63104/5/6 family of jitter attenuating clocks and the SKY62101 ultra-low jitter clock generator.

Keysight's early access to PCIe CEM test tools enables AMD to reach 64 GT/s for next-generation server CPUs.

Innodisk announces the launch of its latest PCIe Gen5 SSD series, designed to meet the OCP Data Center NVMe SSD spec v2.0 and the increasing demands of AI model training, big data analytics, and data-intensive environments.

The three companies will develop technologies for broadband optical SSDs to enhance their suitability for advanced applications that require high-speed transfer of large data, such as generative AI, and will also apply them to proof-of-concept tests for future social implementation.

PCI-SIG has announced that it has reached 1000 member companies, and celebrates this achievement in anticipation of the forthcoming PCIe 7.0 specification, targeted for member release in 2025. 

Designed for enterprise servers and edge data centers, the D2200 series offers outstanding performance with up to 14 GB/s for sequential read and 10 GB/s for sequential write. 

Keysight introduces PCIe Designer, a new product in the ADS product suite that supports simulation workflows based on industry standards for high-speed, high-frequency digital designs.

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.