Items Tagged with 'PCIe'

In the second part of this article series on navigating signal integrity challenges, Abhijit Wander showcases a marked improvement in signal integrity performance, specifically in connector-only scenarios, by transitioning from a microstrip to a stripline footprint design.

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32 dB at 16GHz to -36 dB at 32 GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.

TE is addressing 224G and PCIe Gen 6 signal integrity challenges for the next generation of AI systems, continuing to extend the value of copper, with a combination of passive and active copper cabling solutions.

Samtec, Inc.’s Generate high-speed edge card sockets (HSEC6-DV Series) support 64 Gbps PAM4 (32 Gbps NRZ) applications and are PCIe 6.0 capable. 

With its robust design, integrated Swissbit powersafe PLP technology, and advanced security features, the N3202 is engineered to deliver unmatched reliability and endurance.

PCI-SIG today announced the availability of PCI-SIG ATLs providing PCI Express testing and a process for members to become an official testing lab

Swissbit is expanding its data center solutions portfolio with an SSD range for enterprise server and edge data center applications. The N5200 Enterprise SSD combines reliability, durability, and scalability, making it the ideal choice for mission-critical applications.

Spectrum Instrumentation has extended the M5i flagship series of high speed PCIe digitizers with two new models.

Innodisk announces the release of the first nanoSSD PCIe 4TE3 in response to the increasing demands of edge AI miniature design and high computing performance.

This paper demonstrates a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where one can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.