Items Tagged with 'interposers'

This paper covers a study previously presented at DesignCon 2025 in which a novel SI-PI layout optimization methodology and via routing pattern were developed to address challenges and enable UCIe-xA64 connections to achieve 36 Gbps in Organic Interposer packaging. This summary provides an overview of the challenges, innovations, and methodologies presented in the study, offering solutions for high-speed multi-die system integration.

This paper, previously presented at DesignCon 2025, introduces a comprehensive framework for achieving 12.8 Gbps HBM3/4-to-SoC integration using innovative interposer technologies. This summary covers the key methodologies, findings, and implications of the study, focusing on practical solutions to SI-PI challenges in HBM interfaces.

Teledyne LeCroy has announced the extension of their patented CrossSync PHY technology to support the PCI Express 6.0 specification.

Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s

Teledyne LeCroy announced availability of new PCI Express 6.0 EDSFF interposers based on new Teledyne LeCroy TAP6 technology that reduces signal integrity issues for enhanced probing in high-speed projects.