Impedance has always been the foundation of power integrity. Target Impedance, presented by Larry Smith, provided an intuitive design tool for engineers to determine impedance and expected dynamic voltage noise. “Target Impedance Limitations and Rogue Wave Assessments on PDN Performance” was presented at DesignCon 2015, showing that this relationship was not quite so simple unless the impedance was also flat. At the time, 1 mΩ  impedance was considered very low. 

“How to Measure Ultra-Low Impedance (100uOhm and Lower) PDNs” was presented at EDI CON University in 2018. The presentation concluded with the mathematical relationships in ultra-low impedance measurements, determining the major obstacles and the mathematical solutions. 

The increased core current for the latest AI, data center, and super computing segments made this measurement a lot more complicated, with power distribution network (PDN) impedance now as low as 10 µΩ. Performing this measurement is a challenge, but it is far more difficult than simply performing the measurement. Many, if not most, new boards are liquid-cooled. While some are just refrigerated liquid, others are refrigerated and immersion cooled. Setting up this cooling is not trivial, and some joke that as a power integrity engineer in today’s environment, one needs to be educated in plumbing. Due to this complexity, it would be much more desirable to perform the measurement without cooling, requiring that the measurement be performed very quickly. 

There is an additional challenge: while many are accustomed to measuring small signal impedance with a vector network analyzer (VNA), at these higher currents, there are large signal effects. The impedance is not constant but has a nonlinear load dependency. This is evident in the step load test results shown in Figure 1. The load is stepped from 1500 to 750 A and then from 750 to 0 A. Despite the current change being 750 A in both cases, the voltage excursions are notably different, both in response amplitude and in recovery time. 

Figure 1. The load is stepped from 1500 to 750 A and then 750 to 0 A; note the asymmetrical responses. other more complex step load patterns can be discerned in the upper gray areas.

Therefore, three challenges are presented: how to measure either the small signal response or the large signal response; how to do so extremely quickly so it does not overheat without the attached cooling system; and how to do so for a 10 µΩ active PDN. This article will provide a few viable options, each of which can be performed using the same equipment.

The path here is to use a sophisticated and novel Fast Fourier Transform (FFT) based 3-port measurement (V/I). This method involves applying digitally modulated patterns to create modulated load currents up to 1500 A and recording the resulting power rail voltage perturbations. 

(Re)Establishing the Issues

The final equation in the university paper referenced previously provided the mathematical description of the measurement and the limitations. This compact equation showed that the low frequency ground loop error is the result of the cable shield resistance and the isolator Common Mode Rejection Ratio (CMRR). The equation also included external PDN noise and the measurement noise floor. The theory is proven at the end of this presentation with the measurement of a 20 µΩ resistor.

Despite the appearance that a solution already exists, there are a few shortcomings, one being that this measurement is of a passive resistor. Active power supplies are not quiet; in fact, they can be quite noisy. Equation 1 included noise as a term that has been ignored thus far. The equation indicates requirements of 10 µΩ, so for the future, one needs a plan for measuring well below that.

Using Equation 1, the CMRR required for the measurement is solved as a percent error. In the case of a probe, the ground pin resistance is added to the shield ground in the numerator. The device under test (DUT) magnitude and percent error are in the denominator. Together, these establish the required CMRR.  

The P2102A 2-port probe from the article is then used as an example to measure a 10 µΩ DUT with an uncorrected error of 10%:

This is within the CMRR of the J2114A isolator shown in the article, so theoretically this measurement can be accomplished. However, at this point, one encounters the limitations caused by the power supply noise.

With the caveat that all power rails and voltage regulator models (Vrms) are different, and Constant-On-Time (COT and all derivatives) are noisier than pulse width modulation (PWM) Vrms, Figure 2 shows the power rail noise of the 1500 A ICONIC demo board.

Figure 2. The measurement of a 20 μΩ resistor using a VNA in the 2-port shunt-through configuration.

Figure 3 shows the noise density to be in the range of -80 dBm.

Figure 3. Time domain and spectrum views of the power rail noise for the 1500 A ICONIC demo board.

Using the 2-port shunt-through impedance measurement configuration, the attenuation of the signal, S21, is expressed as:

At 10 µΩ, this is 

This establishes the source power required for the measurement. Using the noise floor of -80 dBm and the signal attenuation of 128 dB:

To be fair, the signal-to-noise ratio (SNR) requires the signal to be at least 6 to 10 dB above this for a decent measurement. Therefore, the minimum will be set at 54 dBm.

Using the Bode 100 VNA (which has a relatively high source power of +13 dBm) in combination with the B-AMP 12 amplifier adds 12 dB gain, resulting in 25 dBm, almost 30 dB short.

How much is 54 dBm?

This requires a 110 Vrms source signal to overcome the noise. Alternatively, the power plane noise of -80 dBm is 22 µVrms. A minimum 6 dB SNR requires a minimum of 44 µVrms to be applied to the DUT. This results in a signal current of: 

The 4.4 Arms signal, multiplied by the Thevenin 25 Ω, results in 110 Vrms, confirming the initial solution.

One could consider developing a 40 dB amplifier, but considering the voltage-related dangers to both the user and to the instruments, this is not a viable solution. While the Bode 100 is fast, measuring with a low receiver bandwidth to minimize the noise is not nearly fast enough to perform this testing without including the refrigeration cooling.

Establishing Boundaries

1. A few ground rules are required before actually defining the measurement solutions. For the purpose of this investigation, use the following conditions:
2. Let the maximum measurement acquisition time of 10 milliseconds (ms) be set arbitrarily. This is generally well within the limits of the Vrms on the power board and the load. 
3. The measurement cannot require equipment other than typical validation equipment already commonly available.
4. The frequency range of the impedance measurement is from 1 to 2 kHz to a few MHz. 
5. Additional post-processing time is allowed; the 10 ms restriction pertains to running a powered board up to and including its maximum load. 

Since most high-power labs use some form of an in-socket load to validate the Vrm performance, this is the tool of choice. Here, a Picotest S2000 high-speed, in-socket, load board solution is used, but devices from other manufacturers should work similarly. The load board is a software-controlled load capable of emulating almost any current profile including pulses, sine waves, and pseudo-random patterns.

With the ground rules established, and after careful consideration, three load current modulation patterns were identified as candidates for this impedance measurement. The Picotest 1500 A ICONIC demo board was selected to power the S2000 load board, since it is very low impedance at about 30 µΩ and is easy to program the different waveforms. Any suitable board and load should be able to perform similarly. 

An added benefit of using the load is that minimal current flows in the instrument cables. While this is a small ground loop, most of the current is limited to the loop through the load and power board. Despite this, a TPR4000 power rail probe with a J2115A coaxial isolator and a P2104A browser tip to connect to the board were used (see Figure 4).

Figure 4. A picture of the ICONIC demo board with the P2104A 1-port browser probe as well as the Tektronix MSO6B scope with a TPR4000 power rail probe in the background. A second cable is monitoring the programmed load pattern.

The three candidate methods for making this measurement are shown next, with a basic description and commentary in Table 1. 

Impulse

The impulse is well-known to have a flat response, or constant amplitude versus frequency, and wide bandwidth. The amplitude at each frequency is set by the pulse amplitude and the pulse duty cycle. The bandwidth is set by the on-time and the impulse repetition frequency, while the minimum frequency and the frequency spacing are set by the impulse repetition rate. This necessitates some compromises to achieve all the goals.

For this example, two sequential double pulses were used. The first two pulses are 1200 A, 5 microseconds (μs) wide and a 500 μs period. The duty cycle is 1%, resulting in an average power less than 10 W. The 5 μs pulse width results in a 3 dB bandwidth less than 100 kHz, which is short of the 1 MHz minimum goal. A second double-pulse is set for a 50 μs period and a 500 ns pulse increasing the bandwidth by an order of magnitude. This also averages less than 10 W. The entire acquisition requires a bit more than 1 ms memory allowing a 2 ms acquisition to capture 1 kHz. A third double-pulse could increase the maximum frequency. The S2000 software interface, showing the double-pulse program, is shown in Figure 5. 

Figure 5. The S2000 software GUI panel shows the program waveform and the details of one of the pulses.

Two separate FFTs are performed after the voltage data is captured: one for the lower frequency pulse pair and one for the higher frequency pulse pair. The raw FFT results are shown in Figure 6. The impedance at each frequency is interpreted from the division of the voltage/current.

Figure 6. Raw FFT results of the lower frequency pulse pair and the calculated impedance from the extraction shows 26.2 μΩ.

The impulse is the simplest measurement, requiring only a single level pulse. Achieving a reasonable amplitude requires large duty cycles, reducing the bandwidth. This is overcome by cascading several double pulses and extracting the FFT from each double-pulse waveform, extending the bandwidth. The post-processing of the FFT data is relatively straightforward from the oscilloscope data, either internally or externally, and it is the lowest average power of all the solutions. 

Swept or Stepped Sine

At the opposite extreme, the swept sine methodology is the slowest of the methods and requires the most post-processing, but also offers the largest signals, allowing measurement of the lowest impedance. Due to the very high sample rate of the controller, insufficient memory was available for the 11-bit sine signal at 1 kHz. This method in any case is included, since the controller sample rate will be made selectable to eliminate this limitation. This example includes nine sequential sine waves starting at 5 kHz and requiring 1.4 ms of run time (see Figure 7). At 1 kHz minimum, this would increase to 7 ms. Since higher frequencies will be required, the time will increase, but not significantly, and it will still easily meet the 10 ms criteria.

Figure 7. The S2000 controller software panel showing the nine sequential sine waves. Each consists of two cycles, and each is a 500 A peak with a 500 A offset for a 0 to 1000 A sine wave.

This example uses nine independent FFTs to demonstrate the first decade of frequencies, though the frequencies are known. Increasing the maximum frequency will increase this to approximately 30 FFTs within the scope. For the purposes of brevity, only one of the raw FFT results (7.5 kHz) is shown in Figure 8. The impedance at each frequency is interpreted from the division of the voltage/current.

Figure 8. This method results in the largest signal, 344 A rms at 7.5 kHz is shown here. Two cycles are used at each frequency to obtain an FFT result.

The stepped sine is the most complex measurement because of the many individual FFTs required; however, this should be simple to automate with each frequency known. As it is all post-processed, the power board is not running aside from the 10 ms of allotted acquisition time. This measurement allows the largest of the signals, but has an average power of 250 W for the measurement duration.

Compact-Discrete Multi-Sine

The third and final candidate is the compact-discrete signal, which is in the class of multi-sine signals. As its name suggests, the single waveform is a complex sum of coherent, non-coincident, discrete sine waves. It has the benefit that it can excite many discrete frequencies with flat response. The signals are larger than the impulse, but this solution requires a high sample rate, high-resolution controller, and load. The process for determining the waveform is highly complex, but it is a built-in selection in the S2000 software controller, or it can be imported from an external CSV file. The GUI panel showing the CSV imported compact-discrete signal is shown in Figure 9.

Figure 9. This compact-discrete signal was imported from a CSV file, but is also available from the pull-down menu for wave segments.

Like the stepped sine, this solution requires many FFTs; however, this method offers simultaneous FFT acquisition, and the FFT frequencies are known such as in the stepped sine solution, making the post-processing simpler. The maximum signal amplitudes are larger than the impulse and smaller than the stepped sine (see Figure 10).

Figure 10. Raw FFT data from the compact multi-signal pattern on the lower right, and the voltage response on the upper right. The equal amplitude current signals are shown in the lower left with a 45 dBm amplitude. The extract impedance is 29 μΩ.

DC Load Line for Comparison

For reference, the resistance was also measured from the load line as the difference in voltage divided by the difference in current. This results in 42.4 milli-V/1500 A or 28 µΩ (see Figure 11).

Figure 11. The load line was measured as the difference in voltage between 0 A and 1500 A, resulting in a load line resistance of 28 μΩ.

The division from the rms voltage and current between the cursors is a slightly higher 15.62 milli-V/507.6 A or 30 µΩ. This is a simple and direct measurement, but is only a DC measurement.

The compact-discrete FFT shows the individual frequencies and the flat response, with each signal being approximately 45 dBm. The individual voltage response to each frequency is also shown here. Again, the high sample rate, high-resolution waveform does not allow reaching as low as 1 kHz, but, as with the stepped sine solution, allowing control of the sample rate in the signal generation panel will eliminate this issue. Since the stepped sine solution requires two cycles of the lowest frequency signal, the measurement requires 2 ms acquisition time for a 1 kHz minimum frequency signal. The maximum frequency is set by the load edge speed and the sample rate of the controller. The load speed bandwidth on this board is approximately 40 MHz and the controller sample rate is 66 MSPS. Halving the controller sample rate would allow nearly full bandwidth with a 1 kHz signal, using the maximum available controller memory.

Conclusions

In this article, three candidate solutions for measuring ultra-low impedance with a maximum of 10 ms were presented. The methods are compared in Table 2.

Though all three methods have pros and cons, they are useful approaches to keep in mind, as each one may serve a purpose at some point in time. All the methods use the same test equipment and setup.

The methods are also compared in Pathwave ADS simulations, which eliminates the effects of noise, measurement errors, and other non-idealities. For this purpose, each signal was applied to a 33 µΩ resistor. The results are shown in Figure 12 and all three were exactly 33.0 µΩ.

Figure 12. All three methods are simulated using Keysight Technologies Pathwave ADS and provide the exact result of 33.0 μΩ.

Figure 13. Discrete current levels are set for measuring efficiency with a 100 μs dwell. The measurement acquisition time is less than 1.5 ms.

In each case, the controller-programmed current (not the measured current) is multiplied by the output voltage, resulting in Equation 1. This product is divided by the product of the 48 V input voltage and the 48 V input current, which is Equation 2. The efficiency result, Equation 3, is shown in Figure 14.

Figure 14. The output current is stepped, and the input power and output power are monitored and divided to provide the efficiency data in a 1.5 ms acquisition without any cooling.

The required dwell time is set by the settling time of the input current. The overshoots in the efficiency curve are the results of the evaluation before the settling time and should not be used.

The total measurement acquisition time for the efficiency measurement is approximately 1.5 ms. Improvement in the quality of the measurement could be obtained by averaging a few measurement samples. Six samples could be performed in a 10 ms acquisition time, allowing the efficiency to be measured without attaching the cooling system.

A special thanks to David Sandler. Without his help in developing this controller software and these waveform algorithms, none of this would be possible.