Anritsu Company (booth #1143) will solidify its position as a global test leader at DesignCon® 2026, February 24-26, in Santa Clara. Anritsu, in collaboration with Tektronix, Teledyne LeCroy, and SiPhx, will conduct live demonstrations, including two on PCI-Express® 6.0 (PCIe® 6.0) and PCI-Express® 7.0 (PCIe® 7.0). Other demonstrations in the Anritsu booth will include 448G interconnect development and broadband S-parameter characterization.
The demonstrations will highlight testing emerging technologies, including:
PCIe 7.0 Test Solution for Initial Verification of Optics and Electrical – Anritsu is teaming with SiPhx, a leading supplier of optical transceivers, to demonstrate PCIe 7.0 over optics. The demos will feature the Anritsu Signal Quality Analyzer-R MP1900A to transmit 64 Gbaud PAM4 signals, as well as the SiPhx 800G LPO Optical Module and 128GT/s TDECQ measurements with Anritsu’s BERTWave™ MP2110A Sampling Oscilloscope.
Additionally, Anritsu will use the Tektronix DPO70000SX ATI Performance Oscilloscope to showcase key transmitter electrical measurements, such as SNDR and RLM at 128 GT/s, through the Tektronix PAMJET Signal Analysis Tool. PCIe over optical links provides higher bandwidth, covers extended distances, and is more energy-efficient, effectively addressing key bottlenecks for AI workloads in data centers.
PCIe 6.0 Stable Link Training – Further highlighting its PCIe testing support, Anritsu will demonstrate stable PCIe 6.0 Link Training and BER measurements using an add-in card. The demonstration, which will be done in collaboration with Teledyne LeCroy, will highlight the capabilities of the MP1900A.
448G Twinax Cable Development – In partnership with Foxconn Interconnect Technology Ltd. (FIT), Anritsu will support next-generation 448G twinax cable development using its VectorStar™ ME7838AX 125 GHz broadband VNA, enabling high-accuracy characterization of advanced high-speed interconnects.
Automated Multiport S-Parameter Measurements for AI/DC Backplanes and Server Cables – This demo will showcase how Anritsu ShockLine™ VNA measurements, combined with ATS (automated test software) driven automation and intelligent switch control, enable efficient, end-to-end S-parameter characterization without repeated manual reconnections. Included in the demo will be a 64-port switch matrix interconnected with Samtec RF cables and configured in an automated setup with the VNA and Anritsu ATS software to conduct signal integrity measurements.
Signal Integrity and BER Analysis – Anritsu’s MP1900A will be integrated with Teledyne LeCroy instrumentation in this demo to deliver coordinated BER testing and signal integrity analysis for high-speed serial interfaces.
High-performance BER Testing – The flexibility and high performance of the MP1900A will be highlighted in this demo. BER testing and signal quality validation will be shown to showcase how the MP1900A can be used in test environments from R&D through production.
Technical Sessions Address Emerging High-speed Designs
Anritsu will conclude DesignCon 2026 with a series of technical sessions on Thursday, February 26. All 45-minute sessions, which will focus on solving design and test challenges associated with emerging high-speed chipsets, components, boards, and systems, will be held in the Great American Ballroom of the Santa Clara Convention Center.
9:00 a.m. – A Scalable, Automated Approach to Signal Integrity Validation for High-speed Interconnects
As high-speed interconnect technologies continue to scale for data center and AI, accurate and repeatable signal integrity characterization is increasingly critical. This presentation introduces a complete ShockLine signal integrity test solution with the MS46524B VNA, integrated with Anritsu’s ATS automation software and a scalable multiport RF switch box architecture.
11:15 a.m. – Testing 224/448 Gbps Electrical/Optical Interfaces to 145GHz and Beyond
AI and data centers are pushing the limits of electrical interfaces, high-speed connectors, and PCBs. The co-existence of optical and electrical presents challenges for engineers developing next-generation transceivers and electrical interfaces/backplanes. In this session, all aspects related to high-speed testing, such as E/E, E/O, O/E , O/O, and multiport, will be addressed.
12:15 p.m. – PCI Express 7.0 Electrical Pathfinding Updates
PCIe technology continues to be a preferred interconnect option that scales with ever-expanding data demands – from AI/ML and high-performance computing applications to hyperscale data centers. In this session, a review of PCIe 7.0 transmitter and receiver tests per the official 1.0 Base Specification will be given. Measurement methodology updates from PCIe 6.0 and early studies of how key measurements extend their capability to expected CEM channels will be presented, as well.
2:15 p.m. – Tx/Rx Validation and Compliance in a Fraction of the Time
This session will cover the latest test methods for High-Speed SerDes Tx, Rx, and return loss compliance and validation. For transmitters, compliance automation, as well as techniques for optimizing the use of oscilloscope equipment in the lab, will be presented. For receivers, Rx calibration and BER/TER testing for NRZ, PAM3, and PAM4 signaling will be discussed. Conducting Tx/Rx return loss, s-parameter measurements efficiently and cost effectively will also be reviewed.
3:15 p.m. - PCIe 6.0 Tx/Rx LEQ Compliance Test
Guidance on how to pass the compliance test at the PCI Workshop with the successful and repeatable stressed eye calibration will be given in the day’s final presentation. Attendees will learn the Tx/Rx LEQ test with the detailed block diagram and the test procedure. In addition, the presentation will address how to troubleshoot the typical problems of Tx/Rx LEQ test and jitter tolerance testing.