Does DC Block Capacitor Location Matter?

January 26, 2021

Sponsored by: EMV


Does DC Block Capacitor Location Matter?

By Gustavo Blando


My high school physics teacher once told me, “If by 22 years old you haven’t discovered anything, I can guarantee you will not be a genius, but don’t despair since you can still be very experienced.” I’m in my 40s and I have not achieved either! Gustavo Blando recently presented “DC Block Capacitor Location (Does It Matter)?” at a Samtec geEEk and spEEk webinar. Here he presents a summary of some of his key points.


Influence of Noise Processes on Jitter and Phase Noise Measurements

By Gary Giust

From the Archives

This article examines the key noise processes involved in measurements of jitter and phase noise, shows how these processes impact test results for various types of test equipment, and provides insight for interpreting these results.


Rohde & Schwarz USA


Five Techniques for Fast, Accurate Power Integrity Measurements

Industry dynamics are driving a decrease in rail voltage values and tighter tolerances across a wide range of rails. Making an accurate ripple measurement on a 1 V rail with 2% tolerance, for example, is difficult on all scopes. Discover how to make accurate power integrity measurements.

Download Rohde & Schwarz USA's app note to learn more.


Richardson Electronics Now Distributor for Isahaya Electronics


Richardson Electronics, Ltd., announced a distribution agreement with Isahaya Electronics. Isahaya products are used in various applications including UPS, induction heating, solar power, wind power, EV charging, and motor drives.


Additional News Highlights

CellBounce Uses SiTime MEMS Timing in Cellular Bridge Solution for Home Security

High Speed, High Accuracy RF Power Measurements Up to 67 GHz with the R&S NRP67S/SN Power Sensors

Passive Plus, Inc. Announces: C.A.P. Online Engineer Tool

Available On-Demand: DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FPGA

EDI CON Online

Didn't get a chance to attend EDI CON Online 2020? This SI/PI Technical Session presented by Benjamin Dannan shows how to model a DDR4 memory channel with an FPGA and demonstrates DDR4 channel and signal integrity analysis for DDR4-3200 speeds. We consider channel characteristics, on-die terminations choices, and equalization controls to optimize our DDR4 signals. The talk includes preliminary analysis that provides channel simulations using Keysight Pathware ADS with the Xilinx Versal FPGA with MICRON memory.

Register now for this on-demand session, it's FREE.


Visit our archived webinars page and watch educational presentations on-demand at your convenience. Browse webinars here.


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