EDI CON Online
Title: DDR4-3200 Channel Modeling and Signal Integrity Analysis Using an FPGA
Date: October 20, 2020
Time: 10am PT / 1pm ET
Presented by: Benjamin Dannan, Consultant, IEEE
DDR4 requires tight specifications for high-speed operation, and then to ensure design margins against a target system bit error rate of 1e-16. DDR4 is now able to reach speeds of 3200 Mbps per pin with an FPGA as the memory controller. This talk shows how to model a DDR4 memory channel with an FPGA and demonstrates DDR4 channel and signal integrity analysis for DDR4-3200 speeds. We consider channel characteristics, on-die terminations choices, and equalization controls to optimize our DDR4 signals. The talk includes preliminary analysis that provides channel simulations using Keysight Pathware ADS with the Xilinx Versal FPGA with MICRON memory.
Benjamin Dannan is an IEEE senior member with a multi-faceted background that includes a wide range of professional engineering and military experiences. His professional engineering experience includes 11 years of designing, developing, and launching production products, ranging from fully autonomous robotic platforms, to pan-tilt-zoom (PTZ) camera video systems, to ground combat vehicles. His design experience includes developing solutions for high-volume, high-reliability, harsh environments, which also entails high-speed PCBA design, mechatronics design, sensor design, and designing solutions that meet EMC susceptibility or radiated EMI requirements. He is a specialist in SI/PI concepts, high-speed design, multi-layered PCB design, vision systems, robotics, as well as has multiple years of experience with EMC product development and certifications to support global product launches. Benjamin also holds a Security+ certification in cybersecurity. He graduated from Purdue University with a BSEE and from The Pennsylvania State University with a Masters of Engineering in Electrical Engineering.
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