Items Tagged with 'DRAM'


Burst Separation 12-19-23.jpg

Understanding Burst Separation for DDR5 System Validation

DDR5 Electrical and Timing Measurement Techniques

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.

Read More

A Brave New World: Simulating DDR5

Eagerly anticipated, the next generation of DRAM technologies (DDR5/LPDDR5) are presently being validated in the lab by leading silicon vendors worldwide. This latest generation has a big surprise in store for hardware engineers and SI specialists that need to simulate such systems. DDR5 will introduce decision feedback equalization (DFE) for the DRAM receiver for the very first time.

Read More