Methodology for Performance Comparison of Center and Edge Sampling in Serial Links

By Hossein Shakiba, Shayan Shahramian, Behzad Dehlaghi, David Cassan, and Davide Tonietto

Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes. Read on to learn more.

Young Professionals Placed in Jeopardy at 2019 EMC Symposium

By Eric Bogatin

On the first day of the 2019 IEEE EMC Symposium, Louann Mlekodaj, Eriko Yamato, Patrick DeRoy and other members of the EMC YP committee organized a Jeopardy game for the Young Professionals Group. As fitting the format of the Jeopardy show at an EMC event, answer categories covered, of course, EMC, SI and PI topics.

Rohde & Schwarz Drives Safety, Security in Urban Air Mobility

Rohde & Schwarz hosted partners and guests from the UAM Ingolstadt Initiative at the company headquarters in Munich for the fourth network meeting. The meeting focused on safety and security technologies needed for Urban Air Mobility (UAM) and attracted industry experts, technology developers, scientific researchers and governmental regulators to discuss the latest developments and future challenges in this fast growing aviation industry.

Harwin Introduces Ready-Made Cable Assemblies for its Datamate Connectors

In order to provide customers with simple plug-and-play solutions, Harwin has now introduced a range of off-the-shelf cable assemblies to accompany its popular Datamate series of high reliability connector components.

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SIJ Publishes July 2019 Issue

Signal Integrity Journal, covering signal integrity, power integrity and EMC/EMI related topics, has published its July 2019 printed magazine issue. The July magazine is available in print (by subscription and at select SI/PI/EMI events) and is also available as an eBook. Don't miss out on the latest...
download the eBook today!

DAY 3 KEYNOTE: 56G/112 Gbps From Front-Panel to the Backplane

EDI CON ONLINE is thrilled to announce its sponsored keynote for Thursday, September 12. Jignesh Shah from Samtec will demonstrate real-world applications in high-performance interconnect design, channel optimization, and alternate system architectures that exceed the demands of next generation data transmission.

Learn more about the details of this keynote talk and
Register for FREE.

DDR/LPDDR Board Design for Signal and Power Integrity

This SI/PI Technical Session on September 12 at 10:30am presented by Shalom-Shlomi Zigdon, will cover factors we must consider including: proper setup/hold time, clean supply voltages, proper termination, trace length matching (including internal length from chip pin until package lead race), topologies for routing VREF, clock and address control, DQS, DQ, power integrity and crosstalk. Samples of DDR4 PCB routing and 6-12 Layers stackup will be demonstrated.

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Measuring and Interpreting Impedance Data

Power integrity engineers have been learning to make VRM impedance measurements to compare to the design goal or “target impedance”. Once the measurement has been performed, it’s important to be able to interpret the data. Is the result good or bad? What do I need to do to improve it? How does the impedance measurement relate to step load response and control loop stability? This webinar addresses all of these topics, providing you with the ability to perform accurate measurements, analyze the results and relate the impedance to step load response and control loop stability. It's not too late to register, join us!

Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.