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DDR/LPDDR Board Design for Signal and Power Integrity

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When

9/12/19 10:30 am to 9/12/19 11:00 am EDT

Contact

Location: Online

Event Description

Title: DDR/LPDDR Board Design for Signal and Power Integrity

Date: September 12, 2019

Time: 7:30am PT / 10:30am ET

Presented by: Shalom-Shlomi Zigdon, iTech iCollege Board Design Academy & Consultant

Abstract:
Recently, printed circuit board (PCB) layouts use a double-data rate (DDR) memory. DDR allows two data bit transitions to occur during a single clock cycle, instead of a single data bit transition doubling its data throughput. The increased speed has caused increased complexity of the PCB layout, bus timing, signal integrity and power integrity.

This talk covers factors we must consider including: proper setup/hold time, clean supply voltages, proper termination, trace length matching (including internal length from chip pin until package lead race), topologies for routing VREF, clock and address control, DQS, DQ, power integrity and crosstalk. Samples of DDR4 PCB routing and 6-12 Layers stackup will be demonstrated.

Presenter Bio:
Shalom-Shlomi Zigdon is an international lecturer on high-speed board design for signal integrity and EMC for R&D teams. He is an EDI CON TAC member and a Chairman of the IEEE EMC & SI/PI Symposium at Israel 2014-2018. Since 1995, he has been the CEO & owner of The College for Board Design and PCB Engineering at Israel [www.itech-icollege.com]. He is a committee member of the following IPC standards committees: IPC-2251 High-Speed Board Design; IPC-2221 PCB Design; IPC-2226 HDI [High-Density Interconnection] PCB Design. Formerly, he served as CEO and VP of Medical Simulator, a hardware engineer at IAI [Israel Aircraft Industries], and a technologist for PCB & MCM at Elbit System. His USA activities include seminars for Intel and PCB Design consultant for signal integrity & EMC for USA companies.

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