December 4, 2018

Sponsored by: EDI CON CHINA



A Study of Forward Error Correction Codes for SAS Channels

By Haitao Xia, Haotian Zhang, Aravind Nayak, Bruce Wilson, and Jun Yao

This paper evaluates the performance of several choices of Reed-Solomon code and shows how a frame-interleaved RS(30,26) code can achieve 1e-15 bit-error rate (BER) in the presence of burst errors. See the authors conclude that, as data rates go higher, current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.

PLDA & Samtec  

PLDA and Samtec Demonstrate PCIe 4.0 Communication over Twinax Cable

PLDA and Samtec announced a demo of their combined PCIe 4.0 solution that delivers full PCIe 4.0 bandwidth (16 GT/s) over copper or optical fiber at minimal cost. The solution is based on a PLDA PCIe 4.0 acquisition board running PLDA’s PCIe 4.0 controller IP combined with Samtec’s FireFly™ Micro Flyover System™.


Keyssa Reinvents I/O to Pave the Path for New Consumer and Industrial Product Designs

Keyssa® announced its Virtual Pipe I/O (VPIO) architecture that enables I/O to scale with processor/memory performance and allows product designers to develop new classes of products. Additionally, Keyssa’s previously announced next-generation solid-state connector, the KSS104M is now in mass production and designed into products slated for launch in 2019.



Rohde & Schwarz


Effective Debugging of USB 3.1 and PCIe Interfaces

By Rohde & Schwarz
Growing data volumes and continually increasing processing and transmission speeds represent major challenges for board designers. The most widely used fast data interfaces are the DDR memory interfaces (DDR2, DDR3 and DDR4, including the low-power variants) and the USB and PCI Express (PCIe) serial communications interfaces. Download the app note to learn more.

Upcoming Webinar

SIMULIA, Dassault Systèmes

Test Vehicles for Benchmarking 3D Full-Wave Solver Performance


High-speed designers who need to design test fixtures as well as backplane designers working on 10-32Gb/s NRZ to 112G PAM-4 can benefit from adopting high-confidence design methodologies when using 3D full-wave solvers. This webinar aims to help you build better test, characterization, and backplane systems, by improving understanding and avoiding the common pitfalls. Learn more and register today.


Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.


The preceding is from Signal Integrity Journal™, owned by Horizon House Publications Inc., at 685 Canton St., Norwood, MA, 02062, USA. We are online at and are also available at 781-769-9750. Copyright © 2018. All Rights Reserved. Your email address has not been given to any Third Parties. You have been selected to receive this email because you opted-in to receive information when you provided your email address to Signal Integrity Journal™. To ensure deliverability of emails from Signal Integrity Journal™, we recommend that you whitelist our domain address:

Unsubscribe/Update Profile | Browser View | Forward to a Friend | Privacy | Subscribe to Signal Integrity Journal