Figure 14 and Figure 15 show the simulation results of RS(52,44) in EMC long channel with different noise properties. Figure 13 is for EMC long channel with AWGN only, where 1e-6 raw BER can achieve 5e-18 after FEC BER. Figure 14 is for EMC long channel with AWGN+Jit+Xtlk combined noise, where 1e-6 raw BER can achieve 5e-17 after FEC BER.
Figure 16 and Figure 17 show the simulation results of RS(52,44) in HP long channel with different noise properties. Figure 15 is for HP long channel with AWGN only, where 1e-6 raw BER can achieve 5e-14 after FEC BER. Figure 16 is for HP long channel with AWGN+Jit+Xtlk combined noise, where 1e-6 raw BER can achieve 4e-15 after FEC BER.
Figure 18 and Figure 19 show the simulation results of RS(52,44) in HP short channel with different noise properties. Figure 17 is for HP short channel with AWGN only, where 1e-6 raw BER can achieve 1e-20 after FEC BER. Figure 18 is for HP short channel with AWGN+Jit+Xtlk combined noise, where 1e-6 raw BER can achieve 4e-20 after FEC BER.
The study in this paper shows that a strong FEC code such as RS(52,44) with error correction capability T=4 can be used in order to achieve after FEC BER around 1e-15 with raw BER = 1e-6. If strong FEC codes are not an option because of implementation complexity, then an interleaving scheme can be used to serve the purpose. With the channels we have simulated, it looks like three-way interleaving performance is very close to two-way interleaving of SAS4 FEC codes.
As data rates go higher with insertion loss becoming bigger, we strongly believe that current 128b/130b encoding is not a good option as the two-bit 01/10 overhead suffers due to its Nyquist pattern property.
 SAS4 standard sas4r06, Working draft American National Standard, Project T10/BSR INCITS 534, revision 06, 11 May 2016.
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Haitao (Tony) Xia is Distinguished Engineer of R&D at Broadcom Ltd, leading the research and development of advanced read channel and Serdes architectures for data storage systems. Dr. Xia served as Chairman of IEEE Data Storage Technical Committee and President of Chinese American Information Storage Society (CAISS) in the past. Before his work at Broadcom/Avago/LSI, Dr. Xia worked at Silicon Valley start-up, Linked-A-Media Devices, on signal processing and coding in the area of magnetic recording channels and non-volatile memories. Dr. Xia has published more than 20 articles in peer-reviewed journals/conferences, and has more than 120 US patent granted to his name. Dr. Xia is an IEEE Senior Member.
Haotian Zhang is a Principal Engineer of R&D at Broadcom Ltd in Longmont, CO., working on the research and development of advanced read channel and Serdes architectures for data storage systems. He holds PhD (2005) degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, and MS (2000) and BS (1997) degrees in electrical engineering from Tsinghua University, Beijing, China. Before his work at Broadcom/Avago/LSI, Dr. Zhang worked at Marvell and Maxtor on signal processing in the area of magnetic recording channels and optical channels..
Aravind Nayak is a Principal Engineer with Broadcom Ltd in Allentown, PA. He holds PhD (2004) and MS (2000) degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, GA, and B. Tech (1999) degree in electrical engineering from the Indian Institute of Technology, Madras, India. His research interest include signal processing for the magnetic recording read channel and SerDes applications.
Bruce Wilson is Director of Architecture at Broadcom's Data Controller Division and worked to advance signal processing and electronics for Data Storage for more than 20 years. Bruce received his Doctorate at Stanford University and has worked at IBM, HGST, LSI and Broadcom.
Jun Yao is currently at Etopus, a Silicon Valley startup to make fast connections. Dr. Yao worked at Broadcom as Senior Engineer and Postdoctoral Researcher at Carnegie Mellon University, PA. He obtained his PhD degree (2013) in electrical and electronic engineering from Nanyang Technological University, Singapore, and bachelor degree (2008) from Harbin Institute of Technology, China. His research interests include signal processing, equalization, phase-locked loop, detection and decoding algorithms for the hard disk drive (HDD) read channel and high-speed Serializer/Deserializer (SerDes) communications.