This paper proposes a model that can serve as a tool for evaluating FEC choices in 200+ Gb/s applications. It allows the comparison of the effect of different inner/outer codes and inner-FEC interleaving schemes on post-FEC BER. It can also be used as a tool for system-level transceiver design, allowing designers to see the impact of design choices on the post-FEC BER efficiently.
What are the optimal methods (and their resulting challenges) to achieve 224/212 Gb/s common electrical I/O (CEI) and Ethernet, the highest speed/data rate per lane electrical input/output (I/Os) and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulation (PAML) vs. channel characteristics at 224 Gb/s.
Interested in performance analysis for 100+ Gb/s per lane PAM4 interfaces? This paper takes a detailed look at high-speed serial link error propagation models and different Ethernet coding schemes as part of FEC performance analysis for 100/200/400 GbE systems with 100+ Gb/s per lane PAM4 interfaces.