Items Tagged with 'Vias'

ARTICLES

Navigating Signal Integrity Challenges Transitioning from PCIe Gen6 to Gen7 Cover 2-20-24.jpg

Navigating Signal Integrity Challenges: Transitioning from PCIe Gen6 to Gen7

With PCIe Gen7 on the horizon, expected to debut around 2025 at a staggering 128 GT/s data rate and a pad-to-pad channel loss budget shift from -32dB at 16GHz to -36dB at 32GHz, this article delves into the evolving performance requirements for Gen7 connectors and details the pivotal design changes needed to meet these demands. The study delves into meticulous design refinements in both the add-in card and baseboard components, addressing challenges such as signal integrity concerns, ground-mode resonances, and the delicate balance between signal performance and mechanical reliability.


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How to Stop Your Differential Vias from Leaking

Can common via structures transfer any data rate or are they limited with a defined bandwidth? If so, what limits its bandwidth? And what can be done when the bandwidth of the signal is greater than the bandwidth of the G-S-S-G structure? This technical feature from Dror Haviv explains.


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40 GHz PCB Interconnect Validation: Expectations vs Reality

What does it take to design PCB interconnects with good analysis-to-measurement correlation up to 40 GHz? Is it doable with typical low-cost PCB materials and fabrication process, typical trace width, via back-drilling and the shortage of space to place the stitching vias? This paper reports lessons learned from validation projects with the goal to build a formal procedure for systematic prediction of interconnect behavior up to 40 GHz. Topics include: selection of test structures, connectors and measurement equipment, and analysis uncertainties.

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Via Characterization and Modeling By Z Input Impedance

In high-speed digital channel design, vias are everywhere and are becoming very crucial elements to the channel performance. Especially with the higher data rate requirements in mobile, networking, and data center applications, the effect of vias in a design is very noticeable. Design engineers have traditionally used time domain reflectometry (TDR) as a tool to characterize and optimize via designs, yet the TDR approach comes with shortcomings such as demanding shorter rise-time step signal or larger bandwidth S-parameters, and inaccurate read-out on the via impedance.

In this article, we propose a simple and effective Z-input impedance method that augments the traditional TDR method for characterizing and optimizing via designs in much faster speed systems.


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