Yuriy Shlepnev

Yuiry Shelpnev argues that simulating a link in isolation from the rest of the board (localization) is probably the most important requirement to simulate interconnects predictably. Read on to understand this important concept.

If we know how to design interconnects that correlate with the measurements for 28 Gbps NRZ, is it going to be a "free lunch" to move to 56 Gbps NRZ? Not so easily, as I learned recently. Read on to see how you can benefit from some analysis and validating your tools.

Design of PCB interconnects for data channels running at bitrate 50 Gbps and beyond is a very challenging problem that requires analyses and measurements over extremely broad frequency bandwidth from DC to 50 GHz and above. This paper shares our experience in building a practical methodology to make predictable 50 Gbps interconnects models.

Models of transmission lines and transitions accurate over 5-6 frequency decades are required to simulate interconnects for serial data channels operating at 10-100 Gbps. Extremely broadband modeling of conductor properties for such high-speed channels is a challenging task. This paper explains physics of the conductor-related signal distortion effects in PCB and packaging interconnects. After reading this paper, you should be able to setup simple experiments in your EDA tool to figure out the limitations and will be sufficiently qualified to ask your EDA tool vendor questions about the accuracy of the conductor modeling effects.