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Measuring the noise on a power rail seems to be a straightforward task. However, there are some basic pitfalls that can cause incorrect, or even downright strange, results. Let's look at one of these challenges: RF pickup. We'll demonstrate the effect of RF pickup on a power-rail measurement, and then we'll show you an effective means of mitigating that effect.
Imec announced that it has demonstrated for the first time a low-cost impingement-based solution for cooling chips at package level. This achievement is an important innovation to tackle the ever-increasing cooling demands of high-performance 3D chips and systems. Learn more.
Microsemi Corporation announced its extremely low inductance package dedicated to high current, low specific on-resistance (RDSon) Silicon Carbide (SiC) MOSFET power modules. The new package, developed specifically for the company’s SP6LI product family, is designed to offer 2.9 nanohenry (nH) stray inductance suitable for SiC MOSFET technology and enable high current, high switching frequency as well as high efficiency.
Signal Integrity Journal compiles some of the best articles on a topic and publishes them all in one easy to access place: an SIJ eBook. These eBooks offer a virtual magazine experience for readers who want to delve deeper into a particular topic. Check out the SI Journal E-book collection today and add some to your virtual bookshelf.
This presentation introduces CST STUDIO SUITE Rule Check®: A smart design rule checking platform that includes knowledge of signal parameters such as rise/fall times, voltage swing, and data rate. CST STUDIO SUITE Rule Check assigns a validated set of geometrical thresholds to each net individually, depending on the signal that it carries (DDR, PCI, Ethernet, USB). Learn how CST STUDIO SUITE Rule Check takes rule checking to the next level.
IoT applications with an embedded controller, sensors, actuators and a wireless interface are proliferating in many applications. Most of these designs are cost driven, low power driven and with a specific form factor. These constraints often require a 2 layer board. By following a few common design guidelines, it's possible to engineer 2-layer IoT boards with remarkably good performance. We'll introduce the seven most important design guidelines useful for all IoT boards which reduce the chance of SI/PI and EMI problems.
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