December 5, 2017

Sponsored by: GigaTest Labs

Analog Devices

Thieving Circuit Boards

Thieving in Printed Circuit Boards

By Lee Ritchey

Lee Ritchey shares some perspective on the topic of thieving in PCBs: what it is, and why it matters to designers.


Microwave-Based Test Method Can Help Keep 3-D Chip Designers’ Eyes Open

Researchers at the National Institute of Standards and Technology (NIST) have invented a new approach to testing multilayered, three-dimensional computer chips that are now appearing in some of the latest consumer devices.


Digitizers allow fast and easy signal processing with new SCAPP Option

Currently digitizers have a bottleneck caused by having to use either the host PC's central processor with 8 or 16 cores or a FPGA that is complex to program. Spectrum Instrumentation has solved this problem with its new SCAPP software option - the Spectrum CUDA Access for Parallel Processing - that opens an easy-to-use yet extremely powerful way to digitize, process and analyze electronic signals.


Mentor Graphics

Discover Unknown PCB Design Issues with DRC

By Mentor Graphics

This free paper by Mentor Graphics discusses how a designer can seamlessly integrate with the PCB design process to find issues that are often missed by current PCB verification methods.



Signal Integrity Journal Announces Its 2018 Editorial Advisory Board


A distinguished Editorial Advisory Board has been assembled to assist the Signal Integrity editorial staff in the article review process and generation of quality content. Meet the EAB team.


Upcoming Webinars

R&S Logo

The 3 Necessary Evils - Discover and Solve PI, SI and EMI Issues Affecting Designs

Today a lot of electronic designs are faced with multiple challenges while integrating digital, analog and RF circuits. To achieve compliance and relevant performance, designers need to characterize power lines and tracks, high speed comms and verify their integrity while not causing any bigger EMI issues. Learn about the relevance of power integrity, signal integrity, and EMC.

R&S Logo

In-Situ De-embedding

Traditional de-embedding methods can give non-causal errors in device-under-test (DUT) results if the test fixture and calibration structure have different impedances. This presentation introduces In-Situ De-embedding (ISD) to address such impedance differences using software instead of hardware, thereby improving de-embedding accuracy while reducing hardware costs.

PCI Express Gen3, Gen4 and Gen5 Physical Layer Test Requirements and Procedures

This webinar will equip engineers with an understanding of the test specifications, detailed test procedures, and optimal test equipment configurations to ensure their products pass PCI Express compliance testing.

Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.

The preceding is from Signal Integrity Journal™, owned by Horizon House Publications Inc., at 685 Canton St., Norwood, MA, 02062, USA. We are online at and are also available at 781-769-9750. Copyright © 2017. All Rights Reserved. Your email address has not been given to any Third Parties. You have been selected to receive this email because you opted-in to receive information when you provided your email address to Signal Integrity Journal™. To ensure deliverability of emails from Signal Integrity Journal™, we recommend that you whitelist our domain address: