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In-Situ De-embedding

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When

12/12/17 11:00 am to 12/12/17 12:00 pm EST

Event Description

Signal Integrity Webinar Series

Title:  In-Situ De-embedding

Date:  December 12, 2017

Time:  8am PT/ 11am ET

Presented by:  Ching-Chao Huang, President - AtaiTec Corporation

Sponsored by:  Rohde & Schwarz USA

Overview: 

Traditional de-embedding methods can give non-causal errors in device-under-test (DUT) results if the test fixture and calibration structure have different impedances. This presentation introduces In-Situ De-embedding (ISD) to address such impedance differences using software instead of hardware, thereby improving de-embedding accuracy while reducing hardware costs. The following topics will be discussed with up to 50+ GHz measurement examples:

  • What is causality
  • What is In-Situ De-embedding (ISD)
  • Comparison of ISD results with simulation and other tools
  • How non-causal de-embedding affects connector compliance testing
  • How to extract accurate PCB trace attenuation that is free of spikes and glitches
  • How to extract a PCB's material property (DK, DF, roughness) by matching all IL, RL, NEXT, FEXT and TDR/TDT of de-embedded PCB traces

Presenter Bio:

Ching-Chao Huang, founder and president of AtaiTec Corporation, has more than 30 years of high-speed design and SI software development experience. He was advisory engineer at IBM, R&D manager at TMA, SI manager at Rambus, and Sr. VP at Optimal. Dr. Huang is an IEEE senior member and he pioneered In-Situ De-embedding (ISD) for causal and accurate de-embedding. He received his BSEE from National Taiwan University and MSEE and PhD from Ohio State University.