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PCI Express Gen3, Gen4 and Gen5 Physical Layer Test Requirements and Procedures


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12/14/17 11:00 am to 12:00 pm EST

Event Description

Signal Integrity Webinar Series

Title:  PCI Express Gen3, Gen4 and Gen5 Physical Layer Test Requirements and Procedures

Date:  December 14, 2017

Time:  8am PT/ 11am ET

Presented by:  Hiroshi Goto, Business Development Manager, Anritsu & Patrick Connally, Technical Marketing Engineer, Teledyne LeCroy

Sponsored by:  Anritsu and Teledyne LeCroy


PCI Express testing can be a daunting prospect; physical-layer testing requires tools with sophisticated protocol-aware capabilities at transfer rates of 8, 16, and up to 32 Gb/s. Anritsu and Teledyne LeCroy provide compliance test coverage with industry-leading signal generation, physical- and protocol-layer analysis and Bit Error Ratio measurement technology.

This webinar will equip engineers with an understanding of the test specifications, detailed test procedures, and optimal test equipment configurations to ensure their products pass PCI Express compliance testing.

Presenter Bios:

Hiroshi Goto has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager.  Mr. Goto holds a Bachelor’s degree in Physics from Aoyama Gakuin University. He resides in the Dallas area and has authored numerous industry application notes and white papers and frequently speaks on the topic of signal integrity.

Patrick Connally joined Teledyne LeCroy in 2013, and works as a Technical Marketing Engineer specializing in high-bandwidth oscilloscopes. He received his PhD in Electrical and Electronic Engineering  from Queen's University Belfast in 2006, and has been working in the test and measurement industry since 2009.