Samtec Inc., will showcase and demonstrate their latest high-performance interconnect and technologies at the PCI-SIG® Developers Conference 2019.
Samtec high-speed technologies for Silicon-to-Silicon optimization will be on display, including new high-speed, high-bandwidth optical, board-to-board and cable-to-board interconnects. 56 Gbps PAM4 and 32 GT/s product demonstrations and technical sessions will also be highlighted.
- Scalable 32 GT/s Silicon Test Platform:
Demonstration of configurable, next-generation GPU-based system combining a cable mesh backplane (AcceleRate® Slim Body Cable Assemblies) and next-generation Edge Rate® High-Speed Edge Card Connector topologies.
- 56 Gbps PAM4 Active Product Demonstrator:
The 56 Gbps PAM4 Active Product Demonstrator showcases Samtec’s comprehensive portfolio of high-performance interconnect in a typical data center chassis application.
1:00 PM Tuesday, June 18, 2019 - Kevin Burt Sr. System Architect – Optical Systems
- Enable PCI Express® (PCIe® ) 5.0 System Design with Ethernet Architectures:
As PCIe technology data rates increase to 32 GT/s, system SI becomes critical. As other interfaces (Ethernet, InfiniBand, etc.) achieve higher data rates, opportunities exist to leverage techniques that optimize power, thermal efficiency and cost-effectiveness across the system. Samtec will explore options enabling PCIe technology system architects to achieve similar results.
11:30 AM Wednesday, June 19, 2019 - Steve Krooswyk Sr. SI Engineer
- 2GT/s Test Platform for AI and ML Implementations:
Confident SI evaluation in emerging AI/ML forms factors and cable mesh topologies requires realistic interconnect stress. Current length extenders and multiple PCIe topologies present challenges for adequate SI evaluation. Samtec will present the advantages of next-generation Scalable 32 GT/s Silicon Test Platforms.
The demonstrations can be seen in the Samtec booth at PCI-SIG Developers Conference 2019 at the Santa Clara (CA) Convention Center. The conference is June 18-19, 2019.