Modeling Other Noise Sources using an Active Model

None of these linear models can account for any of the noise on the Vdd rail from VRM-aggression, which can be caused by an inadequate power-supply rejection ratio (PSRR) and noise on the primary power source, switching noise from the internal VRM operation, or nonlinear transient response from changing current loads.

Any of these effects will generate more noise on the pins of the VRM and appear on the Vdd rail pads if their frequency components are below the pole frequency of the Bandini Mountain. These noise sources will add to the Vdd self-aggression noise caused by Vdd transient currents. In extreme cases, VRM and other aggressor noise can exceed the self-aggression noise tolerance and cause larger problems.

The factors that contribute to these noise sources are often not related to the PDN design features that we optimized to reduce the Vdd self-aggression noise. These factors must be analyzed and addressed independently of design features introduced to reduce the Vdd self-aggression noise.

An accurate VRM model reflects the non-linear properties of transistors and feedback loops that occur when load currents transition from very low to very high values and the VRM is at the limit of its current delivery range. An accurate VRM model also takes into account switching noise and PSRR effects, as well as small- and large-signal impedance effects. Accurate models are required for closed-loop feedback simulations to determine the best circuit elements and parameters for stability analysis. Accurate VRM models are required for optimal VRM design and integration into the entire PDN system.

As an example, a simple switch-mode power supply (SMPS) buck converter schematic is shown in Figure 4. It converts some higher DC voltage to a DC voltage appropriate for CMOS logic, often about 1 V. It involves complex circuitry to sense and regulate the output voltage, monitor current, open and close switches at appropriate times, and maintain stability over different load conditions.

Basically, the top switch remains closed until the working inductor is fully charged with current. The bottom switch is then closed to allow current to continue through the inductor loop while the loop current and energy stored in the working inductor diminishes. Complex circuitry and algorithms enable this class of regulators to function. Simulation and modeling of the SMPS is a major discipline in itself, and significant design efforts and computer resources have been dedicated to these efforts. Ultimately, it is with such models that the interactions of the VRM with the rest of the PDN can be analyzed and each element optimized.



It is important to use a proper VRM model in PI simulations. An ideal voltage source should never be attached to a port of an extracted printed circuit board S-parameter model, as is often done, because it shorts out a significant portion of the PDN with zero impedance.

The ideal voltage source must be isolated from the board power planes and discrete capacitors by an impedance that represents the VRM. Preferably, the VRM model is tuned and correlated to regulator spec sheets and actual VRM measurements. If this information is not available, a 4-element RLRL model with an impedance peak at approximately the right magnitude and frequency may be used. The RLRL parameter values may be determined from the properties of the impedance peak. The VRM model affects the PDN impedance curve in a certain frequency band, often 20 kHz to 20 MHz.

Although linear models for the VRM are critical for optimizing the board-level PDN to manage Vdd self-aggression noise, they cannot provide any insight into noise that originates with the VRM.

For a complete description of the noise in the PDN, including the VRM self-aggression noise, a non-linear model is needed and can be implemented using a state space model.

Figure 5 compares the measured output impedance of a SMPS VRM with the best fit of an RL model, and RLRL model and a more complex active model. We see the value of the RLRL model for impedance modeling and the same performance of the active model, but the active model has the advantage of modeling other noise sources.



[1]         S. Sandler, How to Design for Power Integrity: DC-DC Converter Modeling and Simulation. 2018.

[2]         V. Sriboonlue, L. Smith, J. Mohamed, J. Shin, and T. Michalka, “Novel Parallel Resonance Peak Measurement and Lossy Transmission Line Modeling of 2-T and 3-T MLCC capacitors for PDN Application.”

[3]         H. Barnes, J. Carrel, and S. Sandler, “Power Integrity for 32 Gb/s SERDES Transceivers,” in DesignCon, 2018.

[4]         L. Smith and E. Bogatin, Principles of Power Integrity for PDN Design. Prentice Hall, 2017.

[5]         S. Sun, A. Corp, L. D. Smith, and P. Boyle, “On-Chip PDN Noise Characterization and Modeling,” in Santa Clara, CA, DesignCon, 2010, no. 408, pp. 1–21.

[6]         S. Sandler, "Characterizing and Selecting the VRM," Design Con 2017.