Items Tagged with 'Cadence'

The Cadence^® ChipStack AI Super Agent is the world’s first agentic workflow for automating chip design and verification.

This article describes the use of Cadence’s Sigrity signal and power integrity solution ML optimization algorithm to quickly and efficiently converge on the best set of parameters in a set of IBIS-AMI models. The application of Sigrity was investigated for refining IBIS- AMI parameters to find the optimal set of values to maximize a specific metric.

Leveraging years of stacked BSI sensor production, Tower’s wafer-scale 3D-IC technology unlocks integration of SiPho and EIC processes for emerging applications such as co-packaged optics, including full support by Cadence design tools to the stacked platform technology.

Cadence has achieved a significant milestone by designing and taping out its first-ever system chiplet, marking a groundbreaking advancement in chiplet realization capabilities. 

Spirent Communications has announced a collaboration with Cadence Design Systems, Inc. to deliver a joint networking system-on-chip verification solution that bridges the gap between pre-silicon and post-silicon verification.  

In a commitment to building a culture that fosters inclusion and embraces diverse backgrounds, experiences, and ideas, Cadence offers the Cadence Women in Technology, Black Students in Technology, and Latinx Students in Technology Scholarships for eligible students and interns.

Wild River to discuss its Channel Modeling Signal Integrity Platform, which successfully correlated to Cadence’s Clarity 3D Solver for robust electromagnetic simulation, at CadenceLIVE Silicon Valley.

Recently, Cadence released its Clarity 3D Transient Solver for EMI simulation.  I caught up with Brad Griffin, product management group director for multi-physics system analysis in the Custom IC & PCB Group at Cadence to follow up for some more details.