Bert Simonovich

When starting a new project, board designers are often overwhelmed when trying to choose appropriate diff pair geometry, board material, and stackup to meet high-speed serial link loss budgets. Part of the printed circuit board (PCB) interconnect challenge is modeling transmission lines accurately. 

In the GB/s regime, accurate modeling of insertion loss and phase delay is a precursor to successful high-speed serial link designs. We propose a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance. Transmission lines simulated with a causal version demonstrate increased phase delay and characteristic impedance. By obtaining the dielectric and roughness parameters solely from manufacturers' data sheets, we validate the model through a detailed case study to test its accuracy.

It’s what you don’t know you don’t know that can ruin your day. This paper notes in detailed examples that with today’s high-speed designs, we can no longer restrict our thinking in terms of signal integrity, power integrity or EMC alone. We must consider all three disciplines and become educated about each of them to achieve successful designs.

As Dave Dunham from Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." In order to ensure first time success at these speeds, accurate channel modeling is a prerequisite. This is especially true for long backplane channels.

We worry about via stubs in high-speed designs because they cause unwanted resonant frequency nulls which appear in the insertion loss plot (IL) of the channel. But are all via stubs bad? Well, as with most answers relating to signal integrity, “It depends.”

In the GB/s regime, accurate modeling of conductor loss and phase delay is a precursor to successful high-speed serial link designs. In this paper, a practical method to model effective permittivity and phase delay, due to conductor surface roughness, is presented. By obtaining the dielectric and roughness parameters, solely from manufacturers’ data sheets, phase delay and effective permittivity can now be easily predicted. Detailed case studies and several examples test the model`s accuracy.

It is a well-known fact that electromagnetic radiation can be emitted from the edges of printed circuit boards (PCBs). When a current carrying via passes through two or more reference planes, an EM wave propagates radially away from the via within the cavity.  It is guided by the respective planes; much like a water ripple will propagate radially away from a rain drop hitting a puddle of water. When the wave meets the PCB edge, the two reference planes form a slot antenna and will radiate noise with the potential to generate electromagnetic interference (EMI) to nearby equipment.