Power Integrity

Figure 4

Practical DDR Testing: Compliance, Validation and Debug

DDR memory interfaces are becoming increasingly common, and present a unique set of challenges to those designing high-speed embedded systems.  This article will examine what DDR interface testing is all about, concentrating primarily on the physical layer and solutions to common problems.
Read More
F 3

How Much Capacitance Do We Really Get?

We have to use enough capacitors so that the PDN functions properly. At the same time, to keep cost and size in check, we want to avoid overdesign and not use capacitors unnecessarily. Read on for advice on how to find the balance.


Read More

CST Supports the 2017 TIE+ PCB Design Simulation Contest

Computer Simulation Technology AG (CST), part of SIMULIA, a Dassault Systèmes brand, congratulates Radu Voina of the Technical University of Cluj-Napoca, the winner of the Interconnection Techniques in Electronics (TIE) contest, held at the “Gheorghe Asachi” Technical University of Iasi, Romania.

Read More