May 29, 2018

Sponsored by: Mentor



RFI and Receiver Sensitivity Analysis in Mobile Electronic Devices

By Antonio Ciccomancini Scogna, Hwanwoo Shim, Jiheon Yu, Chang-Yong Oh, Seyoon Cheon, and NamSeok Oh

Receiver sensitivity and noise coupling to antenna are two major concerns when developing mobile devices such as smart phones and tablets. There are various causes of degradation of receiver sensitivity. However, most of the time they are due to the noise generated by digital signal harmonics on printed circuit board (PCB) patterns, which couple to the antennas. This article presents a methodology to predict noise to antenna coupling and antenna desense.


Richardson RFPD Introduces New Board Level Shields from TE Connectivity

Richardson RFPD announced the availability and full design support for a new portfolio of board level shields from TE Connectivity. These new board level shields are stamped one- and two-piece metal cages that help provide isolation of board-level components, minimize crosstalk and reduce EMI susceptibility without impacting system speed.

Silicon Labs & Calnex Solutions  

Silicon Labs and Calnex Simplify SyncE Design and Testing Using Marvell Alaska C 25GbE/100GbE Transceivers

Silicon Labs and Calnex Solutions announced a proven reference design for ITU-T G.8262-compliant Synchronous Ethernet (SyncE) applications at 25G and 100G Ethernet rates. The solution is based on the Marvell® Alaska® C family of high-speed Ethernet transceivers, Silicon Labs’ Si5348 low-jitter network synchronizer clock and the Calnex Paragon-100G test platform. Learn more.




Design and Characterization of SerDes Channels

This whitepaper highlights the key features for SerDes Channel Design in CST STUDIO SUITE® including the new eye diagram tool, demonstrating realistic transmitter and receiver models including jitter, modulation and equalization at both the pre-layout and post-layout stage.

EDI CON USA CFA Closes this Week

EDI CON USA Call for Abstracts Closes this Week!

EDI CON USA 2018 call for papers is open until May 31st. The event is for high speed and high frequency engineers on Oct 17-18 in Santa Clara, CA. The aim of the event is to provide hands-on access to practical design techniques, products, and technologies. More information and to submit abstracts for review by the Technical Advisory Committee here.

Upcoming Webinars


PCB Design Rules that Really Matter

This presentation introduces CST STUDIO SUITE Rule Check®: A smart design rule checking platform that includes knowledge of signal parameters such as rise/fall times, voltage swing, and data rate. CST STUDIO SUITE Rule Check assigns a validated set of geometrical thresholds to each net individually, depending on the signal that it carries (DDR, PCI, Ethernet, USB). Learn how CST STUDIO SUITE Rule Check takes rule checking to the next level.

Rohde & Schwarz  

Best IoT Board Design Practices: Balancing Density, Cost, Low Power, and Mixed Signal

IoT applications with an embedded controller, sensors, actuators and a wireless interface are proliferating in many applications. Most of these designs are cost driven, low power driven and with a specific form factor. These constraints often require a 2 layer board. By following a few common design guidelines, it's possible to engineer 2-layer IoT boards with remarkably good performance. We'll introduce the seven most important design guidelines useful for all IoT boards which reduce the chance of SI/PI and EMI problems.

Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.

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