Silicon Labs and Calnex Solutions today announced a proven reference design for ITU-T G.8262-compliant Synchronous Ethernet (SyncE) applications at 25G and 100G Ethernet rates. The solution is based on the Marvell® Alaska® C family of high-speed Ethernet transceivers, Silicon Labs’ Si5348 low-jitter network synchronizer clock and the Calnex Paragon-100G test platform.

Cisco VNI forecasts mobile data traffic is expected to grow at a compound annual growth rate of 46 percent between 2016 and 2021. This transition is driving service providers to deploy higher capacity 25GbE and 100GbE links to backhaul mobile data from wireless base stations to metro/core optical networks. 4G and 5G networks have stringent requirements for phase and frequency synchronization to mitigate interference and more effectively share user bandwidth between adjacent cell sites. Mobile backhaul and fronthaul networks will use a combination of IEEE® 1588 and SyncE to distribute phase and frequency synchronization across the network. The joint Silicon Labs and Marvell solution enables equipment providers to extend SyncE to their highest speed backhaul and fronthaul networks and design with confidence using a proven solution for packet network synchronization.

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“Carriers and data center operators are responding to the insatiable demand for video streaming and mobile data by transitioning to higher speed Ethernet networks,” said James Wilson, Senior Marketing Director for Silicon Labs’ timing products. “Silicon Labs is excited to partner with Marvell and Calnex to offer a proven, SyncE-compliant solution for 25/50/100/200/400GbE designs.”

The joint solution uses Silicon Labs’ Si5348 low-jitter network synchronizer in combination with the Marvell Alaska C 88X5123 and 88X5113 25GbE/100GbE industrial temperature-capable Ethernet transceivers. The Si5348 synchronizer, a part of Silicon Labs’ growing portfolio of high-performance network synchronization products, has the lowest jitter and a highly integrated clock solution for Synchronous Ethernet. The device’s jitter performance of 100 fs rms (typ) optimizes transceiver performance and helps minimize system-level bit-error rates. The device supports three fully independent, frequency flexible DSPLLs, enabling a single clock IC to support SyncE clock synchronization and clock generation as well as general-purpose timing for FPGAs, processors and other devices.

The solution was tested using the Calnex Paragon-100G, a fully SyncE-compliant test platform that provides automated wander, jitter, transient and IEEE-1588 precision time protocol testing with measurement precision. The overall solution, including the network synchronizer and Ethernet transceiver, was fully tested for compliance with ITU-T G.8262. Test results show that the solution has significant margin to G.8262 Ethernet Equipment Clock (EEC) Option 1 and Option 2 jitter generation and jitter tolerance requirements. The design is optimized to minimize phase transients caused by a protection switch (e.g., a fiber cut). The resulting solution provides significant margin to both current ITU-T G.8262 specifications as well as the more stringent G.8262.1 enhanced EEC standards currently in development.

For a copy of this SyncE compliance report, visit www.silabs.com/synce-reference-design.