Zuken® and XJTAG®, a leader in boundary scan and design for test technology, have entered into a partnership to enhance Zuken’s CR-8000 with a design for test (DFT) capability that will improve test coverage during schematic entry. The capability is based on XJTAG’s DFT Assistant, and will be available later this year as a free plugin for Zuken’s CR-8000 Design Gateway users.
CR-8000 is a native 3D product-centric design platform for PCB-based systems. CR-8000 directly supports architecture design, concurrent multi-board PCB design, chip/package/board co-design and full 3D MCAD co-design. CR-8000 Design Gateway is Zuken’s platform for logical circuit design and verification.
Validate JTAG Chain Connectivity
Increasingly, printed circuit boards (PCBs) are densely populated making it difficult to gain manufacturing test access to pins under many packages, such as ball grid arrays (BGAs). JTAG was designed to enable test access, so an optimized JTAG design can have a positive impact on ROI. Failure to optimize JTAG test coverage at an early design stage can increase manufacturing costs and possibly require a board re-design.
XJTAG DFT Assistant will help to validate correct JTAG chain connectivity while displaying boundary scan access and coverage onto the schematic diagram through full integration with CR-8000 Design Gateway.
Simon Payne, CEO of XJTAG, says: “XJTAG is pleased to be joining Zuken’s solution ecosystem. Companies need to determine early in the design phase how to maximize test coverage using the minimum number of test points, so it is essential to know what JTAG access is available at the schematic stage of the design process. The XJTAG DFT Assistant for Zuken’s CR-8000 Design Gateway will make it easy to see the test access as the design evolves. This allows test engineers to significantly optimize testing before PCBs are produced.”
Bob Potock, Vice President of Marketing at Zuken USA, Inc, says: “Boundary scan technology and XJTAG’s DFT Assistant will enable engineers to build, optimize and measure the chain’s test coverage at the schematic entry stage. For our customers, this enhancement will mean better test coverage that translates into better manufacturing yields and lower costs.”