It is my privilege to introduce myself as the newest Technical Editor for Signal Integrity Journal, a role I take on alongside my full-time position as Senior Director of R&D for Compute, Storage, Optical Transport, and High-Speed Ethernet Test Solutions at VIAVI Solutions.
It has been a journey to get here. I have spent more than 20 years working in electromagnetics and RF engineering. Over the past 16 years, I led engineering teams developing test and measurement instruments and solutions across domains as varied as SAR assessment, antenna characterization, EMC compliance, automotive radar validation, and vector network analysis (VNA) — with frequencies spanning from a few kHz to beyond 300 GHz. I started to see a shift about three years ago, as demand for RF instruments became increasingly driven by signal integrity topics. Today at VIAVI, I sit at the heart of the high-speed digital and AI/data center infrastructure revolution, developing the latest generation of high-speed Ethernet and PCIe test solutions — where signal integrity isn’t a peripheral concern but a central engineering challenge, both for the testers we develop and the products our customers build. With this transition, Signal Integrity Journal feels like a natural home for me to keep learning and help share knowledge.
Speaking of knowledge sharing, I want to sincerely thank my predecessor, Professor Eric Bogatin, for his years of leadership in this role. His contributions to the field of SI/PI are a reference point for the community, and as the past Technical Editor, he helped move this community forward and shape perspectives on where the field is actually heading. These are big shoes to fill, and I don’t take that lightly. I hope to bring the same curiosity and rigor to this role that Eric modeled.
For my first issue as Technical Editor, I am glad to see content that speaks directly to the forces driving today’s industry growth: the race to build out AI and data center infrastructure. 224 Gbps co-packaged copper channels and PCIe Gen 7 are being pushed forward by AI scale-up demands — 1.6 Tbps Ethernet, PCIe 7 at 128 GT/s — and these speeds bring genuinely hard problems: channel design complexity at every transition from cable to PCB, and characterization challenges up to 110 GHz and beyond (coming with the next 448 Gbps technology wave) where the probe influence becomes a first-order effect. At these speeds and frequencies, both simulation and measurement are hard to realize accurately, yet controlling uncertainty and validating models against real hardware is essential to any meaningful design optimization. What I find compelling is that the AI industry is now returning the favor: the same AI tools reshaping design and validation workflows are helping engineers solve the very signal integrity problems standing between us and the next generation of AI infrastructure. It’s a virtuous circle worth watching — and this issue captures it well.
