Keysight is a gold exhibitor at DesignCon 2022 and is committed to working with customers to anticipate test challenges, optimize performance, and accelerate time-to-market of high-speed computing interfaces, data center connections, and consumer electronics.
DesignCon will take place April 5-7 at the Santa Clara Convention Center, Santa Clara, California. If unable to attend Keysight at DesignCon 2022 in person, register and Keysight will be live from DesignCon on April 6th at 1:00 p.m. Pacific Time to view each demo station in just 30 minutes. Contact Geri LaCombe to schedule media briefings and solution demonstrations.
On display at the Keysight booth #1039 will be:
PathWave Design Software
- Memory Designer: PathWave ADS Memory Designer allows two innovations to speed development cycles in memory designs: support for NAND Flash, and CA (Command/Address) Data Bus Pre-Layout Builder. NAND Flash to find all key memory technologies in one platform, and CA (Command/Address) Data Bus Pre-Layout Builder to explore different signal bus design choices to generate parameterized pre-layout representations of complex memory systems.
High-Speed Computing Interface
- PCI Express® (PCIe) 6.0/5.0 Tx Test: A PCIe transmitter test solution designed to assist with increases in digital transmission speed and throughput, which introduces challenges with signal integrity, connector crosstalk, receiver jitter sensitivity, and overall channel insertion loss.
- PCIe 6.0/5.0 Rx Test: Designed to validate a receiver to tolerate significantly attenuated signals up to 64 GT/s with PCIe 6.0. Aggressive equalization techniques help the receiver restore the quality of the transmitted signal, allowing for recovery of the digital information from the PCIe signal.
Data Center Connectivity
- 224G Rx Test: 1.6T receiver test solution characterizing 224 Gbps interfaces offering customers high bandwidth and signal integrity.
- 224G Tx Test: Automated test system for 224G physical layer (PHY) validation, spotlighting signal to noise and distortion ratio (SNDR) and jitter measurements.
- 112G Forward Error Correction (FEC) and Impairment: Compliance test solution designed to integrate FEC constraints into physical design validation for 800GBASE devices and components.
- USB4 & DisplayPort 2.0: Utilizing USB4 and DisplayPort (DP) expertise, demonstrating solutions for USB4 and DP2.0 over a lossy, low-cost, passive cable.
- Signal Integrity Analysis: Demonstrating insight into the transmission of digital data from the transmitter, through the channel interconnects, to the receiver. This addresses hyperscale data center network topologies, which demand extreme bandwidth over the 800G physical layer interconnect components including backplanes, line cards, Ethernet cables, and connectors.
DDR5 Memory Validation
- DDR5 Simulation & Test: Spotlighting measurement science performing DDR5 compliance on a simulated waveform for fast repeatable test and a data repository for quick result analysis and decision making.