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May 21, 2019

Sponsored by: SIJ



Effective Link Equalizations for Serial Links at 112 Gbps and Beyond

By Hsinho Wu, Masashi Shimanouchi, and Mike Peng Li

This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE,  DFE, and FEC equalization schemes for serial links at and above 112 Gbps. Read on to learn more.

News Feature1

Spectrum Introduces 16-Bit AWGs With 8 Channels per Card

Spectrum Instrumentation has used its modular design philosophy to create a solution for customers wanting multi-channel AWGs. Having 8 AWG channels on a single PCIe-card only 168 mm in length offers great new opportunities for very compact and affordable test systems. The addition of the two new 8-channel-cards to Spectrum's latest "65" series of PCIe Arbitrary waveform generators means that, using Spectrum's Star-Hub, up to 80 channels can be fully synchronized in a single PC.

News Feature2

Siglent Introduces New Programmable DC Loads

SIGLENT Technologies has introduced the SDL1000X and SDL1000X-E series of programmable electronic DC Loads, which are designed for battery, solar cell, and power supply testing. The SDL1020X/X-E models offer an input range of 150 V/30 A with 200 W total power dissipation, while the SDL1030X/X-E’s have an input range of 150 V/30 A up-to 300 W.


R&S May SC


Power Supply Rejection Ratio Measurement (PSRR)

Sponsored By Rohde & Schwarz
Power supply design engineers often face the challenge of measuring the power supply rejection ratio or power supply ripple rejection (PSRR) of their design. The PSRR is an important parameter to indicate the power supply’s output stability. It provides information about the influence of input voltage variations on the stability of the output voltage. Download the app note to learn more.


Webinar available on-demand

Analysis and Verification of DDR3/DDR4 Interfaces: Available On-Demand

Hermann Ruckerbauert discusses DDR3/4 DRAM Memory as being one of the last remaining parallel interfaces in current industry standards. It is expected to stay parallel (as the "dinosaur" of interface definitions) for the next generation of memory. Design, verification, and debugging of the interface is a difficult task due to several specialties of DDR signaling. In addition, this webcast should make engineers sensitive where to take a close look during design and verification of a DDR DRAM memory interface. View the on-demand presentation to discover more.


Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience.
Browse webinars here.

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