Title: Analysis and Verification of DDR3/DDR4 Interfaces
Date: November 13, 2018
Time: 8am PT/ 11am ET
Presented By: Hermann Ruckerbauert, owner of EKH - EyeKnowHow
Sponsored by: Mentor, a Siemens Business
DDR3/4 DRAM Memory is one of the last remaining parallel interfaces in current industry standards. It is expected to stay parallel (as the "dinosaur" of interface definitions) for the next generation of memory. Design and especially verification and debugging of the interface is a difficult task due to several specialties of DDR signaling, which we will cover in this webinar:
This short webinar cannot give a detailed solution to all of the issues above, but should make engineers sensitive where to take a close look during design and verification of a DDR DRAM memory interface.
Hermann Ruckerbauer, Owner of 'EKH - EyeKnowHow' has over twenty years of experience in high speed measurement and simulation especially on DRAM related interfaces. EyeKnowHow is serving the industry with consulting, simulation, measurements and training for all kind of high speed serial interfaces. Hermann Ruckerbauer is Keysight “certified engineer” due to his experience in working with Keysights ADS simulation environment. After receiving his Bachelor Degree in Micro System Technology from the University of Applied Science in Regensburg he was doing design analysis and application testing for several memory generations at Siemens/Infineon. His latest activity before founding his own company was the definition of the DDR4 signaling standard within JEDEC for Qimonda. With the background of DRAM internal functionally, system application requirements and high speed signaling he is supporting any kind of high speed interface implementations (e. g. for 10G Ethernet, PCIe, SATA, USB, ..) with focus on memory standards. Holding many patents he was award in 2005 from Infineon in the category 'Outstanding Single Patent' for the patent on the “Temperature dependent Self Refresh” in DDR Memory devices.
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