November 6, 2018

Sponsored by: Noisecom



A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics

By Vladimir Dmitriev-Zdorov, Bert Simonovich, Igor Kochikov

Metal loss is an increasingly important factor affecting design quality in all high-speed applications. As operational frequencies went up, it became evident that formulas ignoring roughness of the metal surface greatly underestimated losses. This paper proposes a causal (physically meaningful) form of the Hammerstad and Cannonball-Huray metal roughness frequency dependent complex correction factor. Compared to the widely used, non-causal form, it considerably increases the inductive component of internal metal impedance.


Rugged Connectors from ERNI Designed for Handheld and Remote Automation Control

ERNI has expanded its SMC Series connector and cable assembly offering to support a wide range of industrial applications. The family of dual row SMC small form 1.27 mm [.050"] pitch connectors are more popular than ever due to multiple connector configuration options.


Maxim Announces Widest Voltage Range and Smallest Footprint Himalaya uSLIC Family Additions

Now engineers designing into applications in factory automation, medical, communications and consumer markets can tap into four new micro-system-level IC (“uSLIC™”) modules from Maxim Integrated Products. The MAXM17552, MAXM15064, MAXM17900 and MAXM17903 step-down DC-DC power modules join Maxim’s portfolio of Himalaya power solutions, providing the widest input voltage range (4 to 60V) with the smallest solution sizes.



Rohde & Schwarz


Radio Equipment Directive for Sound and TV Broadcast Receivers

By Rohde & Schwarz

One of the key differences between the R&TTE directive and the new radio equipment directive (RED) is the inclusion of sound and TV broadcast receivers. The ETSI EN 303 340 standard is applicable to digital terrestrial television broad-cast receivers supporting DVB-T and/or DVB-T2 signals. Download the app note to learn more.

Upcoming Webinars


Analysis and Verification of DDR3/DDR4 Interfaces

DDR3/4 DRAM Memory is one of the last remaining parallel interfaces in current industry standards. It is expected to stay parallel (as the "dinosaur" of interface definitions) for the next generation of memory. Design and especially verification and debugging of the interface is a difficult task due to several specialties of DDR signaling, which will be covered in this webinar.

Noisecom, R&S USA, Signal Microwave

PAM4 Jitter, Noise, and BER Analysis

In this seminar techniques for analyzing the performance of PAM4 transmitters and receivers will be discussed. After a brief review of the PAM4 scheme, we dive into jitter and noise analysis of three eye diagram PAM4 signals including the key transmitter diagnostic and compliance tests. We then turn to receiver tolerance testing for both diagnostics including techniques for generating stressed PAM4 signals and measuring both the symbol and bit error ratios.



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