Items Tagged with 'Clock'


PLL Characterization for Datacommunication Components and Systems Cover 2-27-24.jpg

PLL Characterization for Data Communication Components and Systems

Phase-locked loops (PLL) are used extensively throughout modern electronic systems. In data communication systems, PLLs are used in transmitter clock multipliers and receiver clock recovery circuits. A key performance factor for the PLL is how they manage jitter. A critical PLL metric is the jitter transfer function which is based on the PLL loop bandwidth. There are several measurement methods that can be used to characterize PLL loop bandwidth and jitter transfer. When operating on digital data signals, PLL bandwidth can vary with the data pattern. In this article, Greg Le Cheminant, Keysight Technologies, focuses on test methods that allow operation on data rather than only clock signals provide very high precision and useful insights into PLL behavior.

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What to Expect in a Multi-Drop Bus

In earlier DDR systems, the clock, command, and address signals (here in referred to as C/A) were distributed to multiple DRAMs using a forked topology, in which these signals propagate to all the DRAMs in the system at approximately the same time. The propagation delays on the command and address lines (in such systems) introduced timing skew into the system, limiting the operating frequency of the bus and eventually impacting the performance of these memory systems.

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Phase Noise Aliases as TIE Jitter

Here’s a look at how phase noise converts to time-interval error jitter, which is particularly important to those working on reference clocks for high-speed SERDES or sampling clocks. Read on to see how this can help debug systems to reduce sources of timing noise.

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