I’ve been attending and presenting at DesignCon for 28 years since the first HP High Speed Digital Symposium. And every year, it’s been the same thing, overloaded with too many great talks, too many companies’ latest products to see and too many online friends to finally meet in person.

The only thing that has changed is the “too many” part. Needless to say, the many part has only increased.

I go to DesignCon with the greatest of intentions, a pledge to attend many presentations of friends and experts I want to learn from, of company and customer partners to visit, of time to spend in our booth talking to customer about their challenges, and I end up missing more than half of my planned events because I run into someone in the hallway or in a booth and we get into a discussion neither of us want to leave.

Nevertheless, I naively think that I will visit all the talks and events on my wish list, when in reality, I will consider it a successful DesignCon if I just manage to get to the events in which I am participating.

Here is my naïve wish list of what I think I will attend:

Monday (you thought DesignCon started on Tuesday???) 1 pm to 5 pm, check out the IEEE P370 plug fest. Bring your own test board, or borrow one from the P370 members to test drive a new draft de-embedding process spec. You must reserve your spot ahead of time by signing up here. Check out this description.

Tues 9 am – 11:30, Mike Peng Li’s Jitter Tutorial. Mike is one of the industry gurus on jitter analysis and wrote the definitive book on jitter analysis. I learn something new every time I listen to him.

Tues 12 noon. Keynote- Looking ahead at the future. Full disclosure, I am thrilled to be on the panel that Steve Sandler put together. We will share our opinions and visions of where the electronics industry is going in the next five years and some of the challenges ahead. Get five experts in a room and you will hear six opinions. Bring your own vision of where you think the future is and share with me during the show.

Tues 1:30-4:30 Principles of PDN Design with Larry Smith and Eric Bogatin. This tutorial will be based largely on the recent book we wrote. Full disclosure, I’m going mainly to listen to Larry again, my go-to expert on PDN design.

Tues 4:45 pm: The ever popular jitter panel, hosted by Ransom Stevens. This year the debate is on whether PAM4 is the answer.

Wed: 8:30 am, a Keysight education forum on Single bit response analysis of a channel. Full disclosure, my PhD student Tim Wang Lee is one of the presenters. Ask him some hard questions. I think he will meet any of your challenges. This is also based on a paper published in the SI Journal.

Wed 9-9:45 Tales of a differential pair measurement. I have no idea what this is about but its work by Gustov Blando and Istvan Novak’s group so it is bound to be interesting.

Wed 10:15 EMI debugging by Rhode Schwartz. I always learn something new listening to Mike Schnecker. Premises to be some cool demos.

Wed 11 am: Effective return loss for 112G and 56G PAM4, Rich Mellitz. Rich has a new metric he is proposing to characterize channels based on the single bit response of the system, sort of a modified impulse response. Should be interesting.

Wed 12 noon: Keynote with Todd Hubing, How do we make autonomous vehicles safe enough. Todd is another industry icon. Don’t miss the chance to hear him.

Wed 2:15- 3:15. Chip Head Theater, How interconnects work, Yuriy Shelpnev. I suspect this will be a compilation of Yuriy’s greatest hits of signals and fields animations propagating on interconnects. Pretty cool way of visualizing how interconnects work.

Wed 4:30-5:15, Chip Head Theater, How to keep via to via cross talk from ruining your day, Fadi Deek and Eric Bogatin. We’re going to show some pretty counter intuitive puzzles that arise when thinking about the properties of vias passing through cavities and why you should care. Fadi is my PhD student.

Wed 6:30 pm mEEt and gEEk sponsored by Samtec. Stop by the Samtec booth 841 to get your ticket.

Thurs: 8 am Effective Link equalization methods. This has them all, FFE, CTLE, DFE and FEC.  And it’s with Mike Peng Li’s group at Intel.

Thurs: 9 am : Spatial variation of output impedance on sense point and capacitor placement in power distributions networks. Istvan Novak. Enough said.

Thurs 11 am A NIST traceable kit for evaluating the accuracy of de-embedding algorithms. This is a cool project (full disclosure, I am peripherally on the team). The idea was to create a series of small circuit boards which can be individually measured, connected together, measured as composite structures to compare the de-embedded values from the separately measured values.

Thurs 12 noon Keynote: New Horizons Journey to Pluto. WOW! Can’t wait.

Thurs 3:30 pm Chip Head Theater, Secrets to Successful PDN Measurements, Eric Bogatin. I’m bringing my favorite scope to show off some common mistakes made when measuring PDNs due to their special conditions and how to avoid these artifacts.

Wow! I’m tired already. Please do stop by the SI Journal booth or the Teledyne LeCroy booth and say hi.

And if you want to win a copy of Larry and my PDN book, enter the drawing at the Teledyne LeCroy booth, 515 or the Si Journal booth, T1.

See you there!