DesignCon, the premier highspeed communications and system design conference returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits January 31-February 2, 2023.

Education Highlights
DesignCon’s conference program covers all aspects of electronic design, including signal integrity (SI) power integrity (PI), highspeed link design, and machine learning.

DesignCon attendee interests have moved back to optimizing high-speed link design, which had been surpassed in recent years by sessions covering SI and PI topics at the die, chiplet, interposer, packaging, and system interface levels, as well as on sessions covering power integrity, distribution, and management.

Below are some of the highest-rated sessions by DesignCon’s Technical Program Committee peer reviewers for the upcoming 2023 event:

Strobed or not? A Deep Dive into the Secrets of High Bandwidth 3D Chiplet Interconnect Signaling Design with authors and speakers from AMD. Chiplets are gaining momentum these days and this paper should be very useful for parallel bus and serial link designers and promises to include info on DQS alignment, which is not discussed commonly though it is an important part of the channel performance.

The Influence of EM Field Solver Numerical Solution Space on Measurement Correlation to 50 GHz & Beyond with authors and speakers from Wild River Technology and Cadence Design Systems. This session delves into understanding the impact of boundary conditions on simulations and is useful when interpreting simulation results. This is an important topic that is not often covered.

3D Connection Artifacts in PDN Measurements is a joint effort from engineers at Amazon Project Kuiper, Ampere Computing, Cadence, Oracle, Samtec, and STMicroelectronics and demonstrates a very practical measurement technique struggled with by many engineers.

Managing Differential Via Crosstalk & Ground Via Placement for 40+ Gbps Signaling, presented by engineers from GigaTest Labs, MathWorks, SiGuys, and Xconn Technologies, promises to provide a very useful analysis framework that is transferable to other topologies.

Comprehensive Statistical Analysis of SERDES Links Considering DFE Error Propagation from Ericsson and Siemens EDA engineers. This paper proposes a new methodology to analyze DFE error propagation. The technique should improve simulation accuracy for SerDes links without significantly increasing computation time.

Tutorial – Design & Verification for High-Speed I/Os at 10 to 112 & 224 Gbps with Jitter, Signal Integrity, & Power Optimized presented by engineers from Intel will review the latest design and verification developments, as well as architecture, circuit, and deep submicron process technology advancements for high-speed links.

Panel – The Case of the Closing Eyes: Bridging FEC to Signal Integrity with a lineup of experts from Anritsu, BitifEye, Broadcom, Intel, Keysight, Marvell, and Tektronix will provide a lively debate on the role FEC plays and how it can be impacted by signal integrity challenges and what to do with a testing architecture designed to help find a bridge between FEC and SI.

Panel – PCI Express Specification: A High-Bandwidth, Low-Latency Interface for the Compute Continuum includes speakers from AMD and Intel and provides a technical overview of PCIe 6.0 architecture, a preview of the PCIe 7.0 specification features and benefits, and what’s to come for PCIe technology.
Event Passes & Additional Information
The 2023 event pass will provide more options and more ways to connect with the educational offerings of DesignCon than previous years. Ahead of the event, DesignCon will offer five webinars on its digital platform for those registered for the Santa Clara, Calif., event. These webinars, as well as select sessions recorded at the 2023 event, will be available for review online through February.

Conference passholders will continue to have access to the 14 tracks of education, with more than 100 sessions curated by our 97-person Technical Program Committee. All DesignCon attendees will have access to sessions focused on emerging chips and markets, presented by IEEE Spectrum, at our 2023 event. Additionally, for the third year, DesignCon also adds the Drive World conference as a complimentary track for All-Access and 2-Day passholders, where conference attendees will have access to technical education on automotive electronics and intelligence. In total, DesignCon is offering more than 115 educational sessions.

DesignCon has also added additional networking options for 2023 to complement its popular social events; the Welcome Reception and Booth Bar Crawls. For the first time, DesignCon will present an Emerging Engineer breakfast, aiming to offer connections and support to those engineers with less than 10 years of professional experience. The breakfast will coordinate with educational sessions specifically planned to support engineers emerging in their careers.

Additionally, all attendees have access to daily keynotes, panels, Chiphead Theater presentations, exhibitor-led education, the Engineer of the Year and Best Paper Awards presentations, and the DesignCon expo floor.

Among 120+ exhibitors, DesignCon’s expo floor will present some of the industry’s most influential companies, including host sponsor Amphenol, Cadence, Keysight, Molex, Mouser, Samtec, TE Connectivity, and more. Experts from these companies will be on-site to answer design questions, provide advice on engineering, and present educational demonstrations on the latest in high-speed design tools, technologies, and developments.


DesignCon’s 2023 exhibition is open Wednesday and Thursday, February 1-2; the conference is presented Tuesday, Wednesday, and Thursday, January 31-Februaury 2. Registration is open now. All attendees (conference and expo pass holders) to the in-person event will be entered into a sweepstakes with the opportunity to win a $1,000 gift card or other prizes throughout the event. Health and safety remains a top priority at DesignCon, with information on practices available on the event website. More information on the full event is available on