Increasing data rates in high-speed digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter attenuation. Modern designs often follow a two-stage architecture, consisting of a jitter-attenuator and a frequency-synthesizer stage. Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests. To stimulate the PLL, an additional signal source with ultra low phase noise is required.
By downloading this app note, your contact information will be shared with the sponsoring company, Rohde & Schwarz GmbH & Co.KG and the Rohde & Schwarz entity or subsidiary company mentioned in the imprint of www.rohde-schwarz.com, and you may be contacted by them directly via email or phone for marketing or advertising purposes.