SeriaLink Systems Ltd announces a behavioral model for a 106Gb/s PAM4 ADC-based SerDes in Simulink and IBIS AMI.
In collaboration with MathWorks, SeriaLink Systems announces a behavioral model of a high-speed ADC-based multi-standard SerDes developed with MATLAB and Simulink, a block diagram environment for simulation and model-based design of multidomain and embedded engineering systems. An automated flow configures the model for a desired communication standard using COM reference transceiver parameters. The configuration flow augments the COM parameters with analog design data when necessary.
Using the SerDes toolbox, the model automatically generates dual IBIS AMI models (statistical and time domain). This enables leveraging the signal integrity (SI) simulation infrastructure to explore the SerDes performance beyond COM capabilities, accounting for time-varying and non-linear effects due to CDR, ADC, and non-linearities in the system. The implementation in MATLAB and Simulink allows the model refinement with the design data through the project lifecycle.
“With data rates reaching 106Gb/s, SerDes designers must rely on ADC-based topologies and PAM4 modulation. This fuels the need to account for non-linear and time-varying effects early in the architectural development phase. Our modeling framework expands the simulation capabilities beyond linear COM analysis while maintaining the model flexibility. Furthermore, exporting the models to IBIS AMI with minimum effort facilitates a more efficient interaction between all participants of the ecosystem: SerDes IP providers, component vendors and system integrators,” says Aleksey Tyshchenko, CEO of SeriaLink Systems.
“SerDes designers developed IBIS-AMI models correlated with the silicon results using the SerDes Toolbox, and it took a fraction of the time required by alternative methodologies. Now, thanks to SeriaLink Systems, these designers can also use COM to configure the model and go beyond COM’s limitations,” says Barry Katz, development manager at MathWorks.
The model was configured to represent a 106Gb/s PAM4 ADC-based reference SerDes for IEEE 802.3ck standard, and it was correlated with COM across a set of reference channels. In the linear mode, the model correlates well with COM. As expected, with non-linearities enabled, the model shows the link margin degradation below COM predictions. The model will be presented at DesignCon 2020.
For further information please contact Aleksey Tyshchenko: firstname.lastname@example.org.