We use cookies to provide you with a better experience. By continuing to browse the site you are agreeing to our use of cookies in accordance with our Cookie Policy.
By Torsten Reuschel, Ömer Yildiz, Jayaprakash Balachandran, et al.
While a channel may pass a test, the remaining margin and thus its resilience against geometry or material variation in production may not be observable. However, such variations are critical because they may impede the performance or cause high volume manufacturing (HVM) products to fail. This coalition of authors has developed and demonstrated a polynomial chaos expansion (PCE) flow to analyze a full-featured 100GBASE-KR4 link starting from geometry specification to Channel Operating Margin (COM) margin at the receiver. Read on to see their award winning paper on the subject.
Tektronix introduced two new oscilloscopes to its portfolio: the 3 Series MDO mixed domain oscilloscopes and 4 Series MSO mixed signal oscilloscopes. The new products feature touchscreen user interfaces, the largest and highest resolution displays in their classes and sleek designs for cramped lab benches.
Teledyne LeCroy introduced its WavePulser 40iX high-speed interconnect analyzer, a capable solution for complete interconnect testing and validation. The WavePulser 40iX is the ideal single tool for high-speed hardware designers and test engineers to characterize and analyze interconnects and cables for high-speed serial protocols.
Advertisement
Download The Latest SIJ eBooks
Signal Integrity Journal compiles some of the best articles on a topic and publishes them all in one easy to access place: an SIJ eBook. These eBooks offer a virtual magazine experience for readers who want to delve deeper into a particular topic. Check out the SIJ eBook collection today and add some to your virtual bookshelf.
The Electronic Design Innovation Conference and Exhibition (EDI CON) announced that this year, in conjunction with Microwave Journal (MWJ) and Signal Integrity Journal (SIJ), it will host an online, interactive event for high frequency and high speed design engineers on September 10-12, 2019. The interactive technical sessions will occur at no cost to attendees, and sponsors will have the opportunity to present workshops and keynote sessions as part of the daily schedule.
Focusing on 56+ Gb/s PAM4 applications, we show why accurate measurements of the system S-parameters are now absolutely critical in component design, system implementation, and testing for both compliance and hardware debug. The biggest problems are caused by the channel--its frequency response, loss, and reflections--all of which are best described and evaluated in terms of S-parameters. After a short, conceptual review of differential S-parameters, we discuss ISI (inter-symbol interference) and crosstalk. Equalization of ISI in the presence of FEC presents all new problems and crosstalk becomes a major PAM4 signal impairment. Learn more and register today.
Visit our archived webinars page for educational resources on various design and measurement subjects and view at your convenience. Browse webinars here.
