Eric Bogatin, Signal Integrity Journal Technical Editor
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Eric Bogatin is Technical Editor at Signal Integrity Journal and the Dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an Adjunct Professor at the University of Colorado - Boulder in the ECEE Dept. Eric improves the signal to noise ratio by sorting through all of the information available and finding the best quality content to publish on

Signal Integrity

The Quest for Smoother Copper May Have Reached Its Limit

February 25, 2020

Copper loss is one ingredient in interconnect loss. Surface texture or roughness has long been recognized as adding an excess loss over smooth copper. With the SI-VSP (very smooth profile) copper foils recently introduced by Mitsui Mining&Smelting Co. Ltd. (Mitsui Kinzoku), we may have reached the limits.

A Little Perspective

All high-speed electronic products operating at 1 Gbps and above are influenced by the frequency dependent losses in the interconnects. If you do not take them into account, chances are your product may not work.

These frequency dependent losses can convert a beautiful looking eye at the transmitter into a completely closed eye at the receiver. An example is shown in Figure 1.

Figure. 1 An eye diagram as it would look at the transmitter, TX, and at the receiver, RX, after traveling down a lossy interconnect.

Designing a cost-effective system is a delicate balance between the performance required and the cost in power consumption, dollars, risk, and time. While equalization can open an eye with even as much as −35 dB at the Nyquist, it is at the cost of higher power consumption.

In loss dominated systems, we are coming up against fundamental physics limits of the performance we can get out of the system. When your design is limited by loss, it is important to consider all the options available to achieve a lower loss in the system. Generally, there are only two material options: a lower Df laminate and a copper foil that matches the behavior of ideal copper as close as practical.

These market forces have been driving laminate vendors to offer laminates with lower and lower dissipation factors. The same driving forces have pushed copper foil vendors, and now we are approaching copper foils that have properties nearly the same as expected from ideal copper.

The Role of Copper

The frequency dependence of the series resistance per length of a copper trace depends on three factors:

  • Copper conductivity
  • Line width
  • Surface roughness

The first order factor that influences the frequency dependence to copper loss is the skin depth effect. This causes current to redistribute in a signal trace and return path as frequency increases. This means current flows through a narrower cross section and the resistance goes up.

Above about 3 GHz, the series resistance of copper traces increases more than expected from just skin depth effects. This is related to the copper roughness or surface texture. At higher frequency, surface roughness can more than double the attenuation as expected from ideal smooth copper.

The goal in producing copper foil is to develop a cost-effective process that results in copper smooth enough so it does not add additional loss but is still compatible with laminate chemistry to provide adequate adhesion, mechanical properties, and etching qualities.

In their recently announced copper foil, SI-VSP, Mitsui Kinzoku has gotten close to the ideal smooth copper performance. Figure 2 is an example of the mirror-smooth surface texture of their electro deposited (ED) copper foil compared to a traditional matte surface finish in other ED processes.

This innovation has been the result of new plating chemistries and processes to engineer the grain structure of the electro deposited copper foil.

Figure. 2 Left: an example of traditional ED copper foil, and right: a sample of the VSP Series copper foil with a mirror smooth finish, reflecting a mango, common in Taiwan where this foil is manufactured.

A Visit with Mitsui Kinzoku Engineering Managers

Recently I sat down with Hiroshi Ono, SI engineer, Shinichi Obata, deputy general manager of New Product and Process Development at Mitsui Kinzoku, and Eriko Yamato, FaradFlex Marketing manager for Oak-Mitsui Technologies (see Figure 3.)

Figure. 3 From left to right, Shinichi Obata, Hiroshi Ono, and Eriko Yamato.

In their factory in Taiwan, Mitsui Kinzoku produces 1800 ton of copper foil rolls and sheets per month. All of it is ED. The raw copper stock comes in at one end and cut foil sheets, ready for lamination, come out the other end. The complete process flow is shown in Figure 4.

Figure. 4 The complete process flow from raw copper to finished sheets.

In the ED process, copper is continuously plated on a titanium surfaced drum, rotating a revolution every few minutes. The side in contact with the drum comes off the roller nearly as smooth as the polished drum surface. The side in contact with the solution is usually a rougher surface. This is called the matte, or solution side.

The surface texture of the solution side is controlled by the plating chemistry, organic additives, plating current profile, and drum speed. Proprietary organic additives in the plating bath, and careful control of the other conditions, results in different nodule structure and surface roughness. Figure 5 is an example of four classes of copper roughness on the matte side:

  • Class III is the lowest grade of smoothness
  • VLP is very low profile and high tensile strength
  • S-HTE is super high temperature elongation
  • VSP is very smooth profile

The copper grain size is the primary factor influencing the electrical, mechanical, and texture properties of a copper foil. Different end-use applications have different requirements for the combination of mechanical properties, thermal stability, fine line patterning, rough surface texture for mechanical adhesion, or smooth texture for lower attenuation from roughness. Each grade of foil with its unique grain structure is produced with a different chemistry and has a different cost.

Type III is the most common, general purpose, and lowest cost foil, about 90 percent of all foils manufactured.

VLP foil is used in IC package substrates, with a balance between mechanical properties and fine grain size so it can be patterned in fine lines at acceptable cost.

Figure. 5 Examples of the four families of copper texture created with different plating chemistries that control the grain structure.

Latest Generation of VSP Copper Foil

The SI-VSP foil is the highest cost, but also smoothest surface and offers the lowest loss. The first versions of the VSP foil were introduced in 2012. In the last seven years, advances in the VSP chemistry have been made, and the latest version of the VSP foil, SI-VSP, is just being sampled. The root mean squared (Rz) surface profile of SI-VSP is about 0.5 microns.

The impact on loss from the different nodule structure and resulting surface texture of the different grades of VSP foils is shown in Figure 6.

Figure. 6 Measured insertion loss from identical samples of the four different types of VSP foil, showing the reduced loss with smaller nodule size. The highest loss sample, the MLS-G is in the type III category.

The smoother copper surface has lower loss. As a direct consequence, the mechanical adhesion to laminate surfaces would be reduced. To supplement the mechanical adhesion, three surface treatments are done before the foil leaves the factory.

A nodule treatment is applied to increase bonding to the surface. Then a zinc-chromate alloy is plated on the surface of the copper. This provides a more chemically active surface for better adhesion but does not change the surface texture. Then, silane coupling agents, acting as adhesion promotors, are coated on the surface. These materials, customized for different laminate chemistries, increase the adhesion to the laminate to at least 3 lb/in. of peel strength. They also help in the adhesion of photoresist during the circuit board fabrication process.

The silane coupling adhesion promoter assists in both adhesion to the laminate materials, and, in circuit board fabrication, adhesion of the photo resist. This means better control of line widths and when needed, finer lines can be etched.

Each of the different grades of VSP foil have a different surface texture, a different contribution to excess roughness loss, and a different cost. This allows a finer balance in the cost-performance tradeoff when selecting the lowest cost foil that has acceptably low loss. This is also another reason why accurate modeling tools are important for navigating not just the performance of interconnect structures, but also the cost-performance balance.


With the new SI-VSP copper foils being introduced, copper loss has reached its limits. The only direction to head to reduce copper loss is wider lines. This will become an important lever in the cost performance tradeoff in the move toward higher data rates.

Article was published in the SIJ January 2020 Print Issue, Design Tips: Page 44.




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